arm64: dts: renesas: r9a08g046: Add scif{1..5} device nodes

Add scif{1..5} device nodes to RZ/G3L ("R9A08G046") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260505070206.7932-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 02a3029c058e2fdc050ad6b8e18f6a9bbf2dada1..19f2c9f29f5cb7073b4883276731285a1428e0f0 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -166,6 +166,96 @@
                        status = "disabled";
                };
 
+               scif1: serial@100ac400 {
+                       compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
+                       reg = <0 0x100ac400 0 0x400>;
+                       interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "eri", "rxi", "txi",
+                                         "bri", "dri", "tei";
+                       clocks = <&cpg CPG_MOD R9A08G046_SCIF1_CLK_PCK>;
+                       clock-names = "fck";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G046_SCIF1_RST_SYSTEM_N>;
+                       status = "disabled";
+               };
+
+               scif2: serial@1004c000 {
+                       compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
+                       reg = <0 0x1004c000 0 0x400>;
+                       interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "eri", "rxi", "txi",
+                                         "bri", "dri", "tei";
+                       clocks = <&cpg CPG_MOD R9A08G046_SCIF2_CLK_PCK>;
+                       clock-names = "fck";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G046_SCIF2_RST_SYSTEM_N>;
+                       status = "disabled";
+               };
+
+               scif3: serial@1004c400 {
+                       compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
+                       reg = <0 0x1004c400 0 0x400>;
+                       interrupts = <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "eri", "rxi", "txi",
+                                         "bri", "dri", "tei";
+                       clocks = <&cpg CPG_MOD R9A08G046_SCIF3_CLK_PCK>;
+                       clock-names = "fck";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G046_SCIF3_RST_SYSTEM_N>;
+                       status = "disabled";
+               };
+
+               scif4: serial@1004c800 {
+                       compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
+                       reg = <0 0x1004c800 0 0x400>;
+                       interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "eri", "rxi", "txi",
+                                         "bri", "dri", "tei";
+                       clocks = <&cpg CPG_MOD R9A08G046_SCIF4_CLK_PCK>;
+                       clock-names = "fck";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G046_SCIF4_RST_SYSTEM_N>;
+                       status = "disabled";
+               };
+
+               scif5: serial@1004e000 {
+                       compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
+                       reg = <0 0x1004e000 0 0x400>;
+                       interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "eri", "rxi", "txi",
+                                         "bri", "dri", "tei";
+                       clocks = <&cpg CPG_MOD R9A08G046_SCIF5_CLK_PCK>;
+                       clock-names = "fck";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G046_SCIF5_RST_SYSTEM_N>;
+                       status = "disabled";
+               };
+
                i2c0: i2c@100ae000 {
                        reg = <0 0x100ae000 0 0x400>;
                        #address-cells = <1>;