drm/i915: Remove i915_reg.h from intel_fifo_underrun.c

Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
free from including i915_reg.h.

v2: Move GEN7_ERR_INT regs to display header (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-17-uma.shankar@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9a7005e125a9de85e07429c8191df6f6de36e8d8..dcb8cab7b30b7ce40874d803e2cf9c5306bc91eb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -82,6 +82,29 @@
 #define   DERRMR_PIPEC_VBLANK          (1 << 21)
 #define   DERRMR_PIPEC_HBLANK          (1 << 22)
 
+#define GEN7_ERR_INT   _MMIO(0x44040)
+#define   ERR_INT_POISON               (1 << 31)
+#define   ERR_INT_INVALID_GTT_PTE      (1 << 29)
+#define   ERR_INT_INVALID_PTE_DATA     (1 << 28)
+#define   ERR_INT_SPRITE_C_FAULT       (1 << 23)
+#define   ERR_INT_PRIMARY_C_FAULT      (1 << 22)
+#define   ERR_INT_CURSOR_C_FAULT       (1 << 21)
+#define   ERR_INT_SPRITE_B_FAULT       (1 << 20)
+#define   ERR_INT_PRIMARY_B_FAULT      (1 << 19)
+#define   ERR_INT_CURSOR_B_FAULT       (1 << 18)
+#define   ERR_INT_SPRITE_A_FAULT       (1 << 17)
+#define   ERR_INT_PRIMARY_A_FAULT      (1 << 16)
+#define   ERR_INT_CURSOR_A_FAULT       (1 << 15)
+#define   ERR_INT_MMIO_UNCLAIMED       (1 << 13)
+#define   ERR_INT_PIPE_CRC_DONE_C      (1 << 8)
+#define   ERR_INT_FIFO_UNDERRUN_C      (1 << 6)
+#define   ERR_INT_PIPE_CRC_DONE_B      (1 << 5)
+#define   ERR_INT_FIFO_UNDERRUN_B      (1 << 3)
+#define   ERR_INT_PIPE_CRC_DONE_A      (1 << 2)
+#define   ERR_INT_PIPE_CRC_DONE(pipe)  (1 << (2 + (pipe) * 3))
+#define   ERR_INT_FIFO_UNDERRUN_A      (1 << 0)
+#define   ERR_INT_FIFO_UNDERRUN(pipe)  (1 << ((pipe) * 3))
+
 #define VLV_IRQ_REGS           I915_IRQ_REGS(VLV_IMR, \
                                              VLV_IER, \
                                              VLV_IIR)

diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index b413b3e871d826bc7fef187b0f774a19c15038ae..bf047180def9f558bc7ab7b5b5ad3244043d7612 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -29,7 +29,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_irq.h"
 #include "intel_display_regs.h"

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3a54b31bc072edbb54cd5256f1aed2fc6c40b4d8..5cb53a8c451a1c5891003f287887f3347c410800 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -325,29 +325,6 @@
 #define GEN7_MEDIA_MAX_REQ_COUNT       _MMIO(0x4070)
 #define GEN7_GFX_MAX_REQ_COUNT         _MMIO(0x4074)
 
-#define GEN7_ERR_INT   _MMIO(0x44040)
-#define   ERR_INT_POISON               (1 << 31)
-#define   ERR_INT_INVALID_GTT_PTE      (1 << 29)
-#define   ERR_INT_INVALID_PTE_DATA     (1 << 28)
-#define   ERR_INT_SPRITE_C_FAULT       (1 << 23)
-#define   ERR_INT_PRIMARY_C_FAULT      (1 << 22)
-#define   ERR_INT_CURSOR_C_FAULT       (1 << 21)
-#define   ERR_INT_SPRITE_B_FAULT       (1 << 20)
-#define   ERR_INT_PRIMARY_B_FAULT      (1 << 19)
-#define   ERR_INT_CURSOR_B_FAULT       (1 << 18)
-#define   ERR_INT_SPRITE_A_FAULT       (1 << 17)
-#define   ERR_INT_PRIMARY_A_FAULT      (1 << 16)
-#define   ERR_INT_CURSOR_A_FAULT       (1 << 15)
-#define   ERR_INT_MMIO_UNCLAIMED       (1 << 13)
-#define   ERR_INT_PIPE_CRC_DONE_C      (1 << 8)
-#define   ERR_INT_FIFO_UNDERRUN_C      (1 << 6)
-#define   ERR_INT_PIPE_CRC_DONE_B      (1 << 5)
-#define   ERR_INT_FIFO_UNDERRUN_B      (1 << 3)
-#define   ERR_INT_PIPE_CRC_DONE_A      (1 << 2)
-#define   ERR_INT_PIPE_CRC_DONE(pipe)  (1 << (2 + (pipe) * 3))
-#define   ERR_INT_FIFO_UNDERRUN_A      (1 << 0)
-#define   ERR_INT_FIFO_UNDERRUN(pipe)  (1 << ((pipe) * 3))
-
 #define FPGA_DBG               _MMIO(0x42300)
 #define   FPGA_DBG_RM_NOCLAIM  REG_BIT(31)