RISC-V: Add Linux hwprobe mappings for existing extensions

Upstream Linux defines hwprobe bits in RISCV_HWPROBE_KEY_IMA_EXT_0
for the following extensions: supm, zicntr, zihpm, zfbfmin, zvfbfmin,
zvfbfwma, zicbom, zaamo, zalrsc, zabha, zalasr, zicbop, zilsd, zclsd,
and zicfilp.

GCC already supports these extensions, and previous patches add the
matching C API feature-bit metadata.  Copy the upstream Linux bit
assignments and map them directly to the matching feature bits.

This patch does not synthesize summary or implied extension bits, and
it does not add new ISA support.  The PR #185 feature bits depend on
riscv-c-api-doc PR #185.

libgcc/ChangeLog:

	* config/riscv/feature_bits.c (RISCV_HWPROBE_EXT_SUPM,
	RISCV_HWPROBE_EXT_ZICNTR, RISCV_HWPROBE_EXT_ZIHPM,
	RISCV_HWPROBE_EXT_ZFBFMIN, RISCV_HWPROBE_EXT_ZVFBFMIN,
	RISCV_HWPROBE_EXT_ZVFBFWMA, RISCV_HWPROBE_EXT_ZICBOM,
	RISCV_HWPROBE_EXT_ZAAMO, RISCV_HWPROBE_EXT_ZALRSC,
	RISCV_HWPROBE_EXT_ZABHA, RISCV_HWPROBE_EXT_ZALASR,
	RISCV_HWPROBE_EXT_ZICBOP, RISCV_HWPROBE_EXT_ZILSD,
	RISCV_HWPROBE_EXT_ZCLSD, RISCV_HWPROBE_EXT_ZICFILP): Define.
	(__init_riscv_features_bits_linux): Set feature bits from the
	corresponding upstream Linux hwprobe bits.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

diff --git a/libgcc/config/riscv/feature_bits.c b/libgcc/config/riscv/feature_bits.c
index 2ac9b567acb636ee1b2aadd5f09abaa5795fc745..367473050b4236e3286e9be2c6e80b55babd1178 100644 (file)
--- a/libgcc/config/riscv/feature_bits.c
+++ b/libgcc/config/riscv/feature_bits.c
@@ -245,6 +245,21 @@ struct {
 #define RISCV_HWPROBE_EXT_ZCF    (1ULL << 46)
 #define RISCV_HWPROBE_EXT_ZCMOP  (1ULL << 47)
 #define RISCV_HWPROBE_EXT_ZAWRS  (1ULL << 48)
+#define RISCV_HWPROBE_EXT_SUPM   (1ULL << 49)
+#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 50)
+#define RISCV_HWPROBE_EXT_ZIHPM  (1ULL << 51)
+#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 52)
+#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 53)
+#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 54)
+#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 55)
+#define RISCV_HWPROBE_EXT_ZAAMO  (1ULL << 56)
+#define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
+#define RISCV_HWPROBE_EXT_ZABHA  (1ULL << 58)
+#define RISCV_HWPROBE_EXT_ZALASR (1ULL << 59)
+#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 60)
+#define RISCV_HWPROBE_EXT_ZILSD  (1ULL << 61)
+#define RISCV_HWPROBE_EXT_ZCLSD  (1ULL << 62)
+#define RISCV_HWPROBE_EXT_ZICFILP (1ULL << 63)
 #define RISCV_HWPROBE_KEY_CPUPERF_0 5
 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
 #define RISCV_HWPROBE_MISALIGNED_EMULATED (1ULL << 0)
@@ -412,6 +427,21 @@ static void __init_riscv_features_bits_linux ()
   SET_FROM_IMA_EXT (ZCF);
   SET_FROM_IMA_EXT (ZCMOP);
   SET_FROM_IMA_EXT (ZAWRS);
+  SET_FROM_IMA_EXT (SUPM);
+  SET_FROM_IMA_EXT (ZICNTR);
+  SET_FROM_IMA_EXT (ZIHPM);
+  SET_FROM_IMA_EXT (ZFBFMIN);
+  SET_FROM_IMA_EXT (ZVFBFMIN);
+  SET_FROM_IMA_EXT (ZVFBFWMA);
+  SET_FROM_IMA_EXT (ZICBOM);
+  SET_FROM_IMA_EXT (ZAAMO);
+  SET_FROM_IMA_EXT (ZALRSC);
+  SET_FROM_IMA_EXT (ZABHA);
+  SET_FROM_IMA_EXT (ZALASR);
+  SET_FROM_IMA_EXT (ZICBOP);
+  SET_FROM_IMA_EXT (ZILSD);
+  SET_FROM_IMA_EXT (ZCLSD);
+  SET_FROM_IMA_EXT (ZICFILP);
 
   for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; ++i)
     __riscv_feature_bits.features[i] = features[i];