drm/{i915, xe}: Extract pcode definitions to common header

There are certain register definitions which are commonly shared
by i915, xe and display. Extract the same to a common header to
avoid duplication.

Move GEN6_PCODE_MAILBOX to common pcode header to make intel_cdclk.c
free from including i915_reg.h.

v3: Include pcode header as required, instead in i915_reg.h (Jani)

v2: Make the header granular and per feature (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-6-uma.shankar@intel.com

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 0caaea2e64e18d9c14df16a68539788bcec4d8ab..8658872ed86f67b48054d4c09ba2e0733a2028f8 100644 (file)
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -6,6 +6,7 @@
 #include <linux/debugfs.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "hsw_ips.h"
 #include "i915_reg.h"

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 8d84445c69f1bdaa7880c882537a4eebe034e161..618da1dfb67153e0376af67c2ff538f4efd17fcd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_atomic_state_helper.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_bw.h"

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9217050a76e0ec7bed5caf65ee79e30fe65e8bbe..29d90d612bb25cb5a9409403d6c35b4cf5411b50 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -27,9 +27,9 @@
 
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_audio.h"
 #include "intel_cdclk.h"

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 06adf6afbec0aee9290686908b7a807d027664dd..cb9256f72aa9ada5720fd19b25e6c0bc1fd125cf 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -7,6 +7,7 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_backlight_regs.h"

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 78f707b00550adab84e453245230ca02f59120ce..45c4313e6900e694bd27dc4e37c0dbe22d2569b2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -6,6 +6,7 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_backlight_regs.h"

diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
index 3b9879714ea9c0c91f35ae74082d3028bf5c0cb2..61aefe77f90fdf3aa83704a8bfbd6ac9662e46d6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -7,6 +7,7 @@
 
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_display_core.h"

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b7479ced7871439acd200bd8f51c9d035fac0eea..c96f51d881862fa74b7b623e2af6d2303df7e20c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -17,6 +17,7 @@
 #include <drm/display/drm_hdcp_helper.h>
 #include <drm/drm_print.h>
 #include <drm/intel/i915_component.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_connector.h"

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index b41da10f0f85f25c9f5c65de6341fae2c791b6e8..1455ea068d221eabffd9fbb91f6b2eb1813deae5 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -7,6 +7,7 @@
 
 #include <drm/drm_blend.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "i9xx_wm.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 96411f357f5d76808d5364cc80e6e748da231f65..1b9cb70fc64162949c45678f52d748e64a3c91ee 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -8,6 +8,7 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_drv.h"
 #include "i915_reg.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 1154cd2b7c342bfff03fe2ad88b1d87fcd6a31af..a48601395dce18763ccb86b752fc404f73534c84 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -7,6 +7,8 @@
 #include <linux/sysfs.h>
 #include <linux/printk.h>
 
+#include <drm/intel/intel_pcode_regs.h>
+
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "i915_sysfs.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
index 1d19c073ba2ec62b4a77708005a9c31cc5381d92..bcd707e3d4364d295c46f22d1523ff86fd8a06d3 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -6,6 +6,8 @@
 #include <asm/tsc.h>
 #include <linux/cpufreq.h>
 
+#include <drm/intel/intel_pcode_regs.h>
+
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_gt.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 286d49ecc449447c9edac7e7d4e1293c5becf1dc..942ac1ebeceef0098c2490a9141dd82b0043446b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -7,6 +7,7 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "display/vlv_clock.h"
 #include "gem/i915_gem_region.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 90b7eee78f1f1c0ae8bf5d35d8fbcdbd86d928c7..844f2716a386b117b0ec737ddba5835d8a5c019a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -7,6 +7,7 @@
 
 #include <drm/intel/i915_drm.h>
 #include <drm/intel/display_parent_interface.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "display/intel_display_rps.h"
 #include "display/vlv_clock.h"

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6f860c320afc3beaaa75dc1075b026cf68848459..2e9d9d0638ae7273e17031f317a9c9a5c020a11d 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -40,6 +40,7 @@
 
 #include <drm/display/drm_dp.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index c01a35ecfa2fe6e43759c924f834831aed53002c..6d8fbf845bc2e7e3b7e0e881a3fb0f354284c58c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -48,6 +48,7 @@
 #include <drm/drm_probe_helper.h>
 #include <drm/intel/display_member.h>
 #include <drm/intel/display_parent_interface.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "display/i9xx_display_sr.h"
 #include "display/intel_bw.h"

diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index 7dfe1784153f68992b550960cd3c85cbe5196836..a94f26e3b6bf1f4ced788e5b9a01bef7ad316569 100644 (file)
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -9,6 +9,8 @@
 #include <linux/types.h>
 #include <linux/units.h>
 
+#include <drm/intel/intel_pcode_regs.h>
+
 #include "i915_drv.h"
 #include "i915_hwmon.h"
 #include "i915_reg.h"

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 26e5504dbc67a7e4c77b813ed210288573545552..bb87af7d3c220025d6e6b8e413832c7b0323e36c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -957,106 +957,6 @@
 #define    EDRAM_WAYS_IDX(cap)                 (((cap) >> 5) & 0x7)
 #define    EDRAM_SETS_IDX(cap)                 (((cap) >> 8) & 0x3)
 
-#define GEN6_PCODE_MAILBOX                     _MMIO(0x138124)
-#define   GEN6_PCODE_READY                     (1 << 31)
-#define   GEN6_PCODE_MB_PARAM2                 REG_GENMASK(23, 16)
-#define   GEN6_PCODE_MB_PARAM1                 REG_GENMASK(15, 8)
-#define   GEN6_PCODE_MB_COMMAND                        REG_GENMASK(7, 0)
-#define   GEN6_PCODE_ERROR_MASK                        0xFF
-#define     GEN6_PCODE_SUCCESS                 0x0
-#define     GEN6_PCODE_ILLEGAL_CMD             0x1
-#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
-#define     GEN6_PCODE_TIMEOUT                 0x3
-#define     GEN6_PCODE_UNIMPLEMENTED_CMD       0xFF
-#define     GEN7_PCODE_TIMEOUT                 0x2
-#define     GEN7_PCODE_ILLEGAL_DATA            0x3
-#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND     0x4
-#define     GEN11_PCODE_LOCKED                 0x6
-#define     GEN11_PCODE_REJECTED               0x11
-#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
-#define   GEN6_PCODE_WRITE_RC6VIDS             0x4
-#define   GEN6_PCODE_READ_RC6VIDS              0x5
-#define     GEN6_ENCODE_RC6_VID(mv)            (((mv) - 245) / 5)
-#define     GEN6_DECODE_RC6_VID(vids)          (((vids) * 5) + 245)
-#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ    0x18
-#define   GEN9_PCODE_READ_MEM_LATENCY          0x6
-#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK    REG_GENMASK(31, 24)
-#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK    REG_GENMASK(23, 16)
-#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK    REG_GENMASK(15, 8)
-#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK    REG_GENMASK(7, 0)
-#define   SKL_PCODE_LOAD_HDCP_KEYS             0x5
-#define   SKL_PCODE_CDCLK_CONTROL              0x7
-#define     SKL_CDCLK_PREPARE_FOR_CHANGE       0x3
-#define     SKL_CDCLK_READY_FOR_CHANGE         0x1
-#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE      0x8
-#define   GEN6_PCODE_READ_MIN_FREQ_TABLE       0x9
-#define   GEN6_READ_OC_PARAMS                  0xc
-#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO       0xd
-#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO  (0x0 << 8)
-#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)        (((point) << 16) | (0x1 << 8))
-#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO  ((0) | (0x2 << 8))
-#define   DISPLAY_TO_PCODE_CDCLK_MAX           0x28D
-#define   DISPLAY_TO_PCODE_VOLTAGE_MASK                REG_GENMASK(1, 0)
-#define          DISPLAY_TO_PCODE_VOLTAGE_MAX          DISPLAY_TO_PCODE_VOLTAGE_MASK
-#define   DISPLAY_TO_PCODE_CDCLK_VALID         REG_BIT(27)
-#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID    REG_BIT(31)
-#define   DISPLAY_TO_PCODE_CDCLK_MASK          REG_GENMASK(25, 16)
-#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK     REG_GENMASK(30, 28)
-#define   DISPLAY_TO_PCODE_CDCLK(x)            REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
-#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)       REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
-#define   DISPLAY_TO_PCODE_VOLTAGE(x)          REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
-#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
-               ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
-               (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
-               (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
-#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG      0xe
-#define     ICL_PCODE_REP_QGV_MASK             REG_GENMASK(1, 0)
-#define     ICL_PCODE_REP_QGV_SAFE             REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
-#define     ICL_PCODE_REP_QGV_POLL             REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
-#define     ICL_PCODE_REP_QGV_REJECTED         REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
-#define     ADLS_PCODE_REP_PSF_MASK            REG_GENMASK(3, 2)
-#define     ADLS_PCODE_REP_PSF_SAFE            REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
-#define     ADLS_PCODE_REP_PSF_POLL            REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
-#define     ADLS_PCODE_REP_PSF_REJECTED                REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
-#define     ICL_PCODE_REQ_QGV_PT_MASK          REG_GENMASK(7, 0)
-#define     ICL_PCODE_REQ_QGV_PT(x)            REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
-#define     ADLS_PCODE_REQ_PSF_PT_MASK         REG_GENMASK(10, 8)
-#define     ADLS_PCODE_REQ_PSF_PT(x)           REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
-#define   GEN6_PCODE_READ_D_COMP               0x10
-#define   GEN6_PCODE_WRITE_D_COMP              0x11
-#define   ICL_PCODE_EXIT_TCCOLD                        0x12
-#define   HSW_PCODE_DE_WRITE_FREQ_REQ          0x17
-#define   DISPLAY_IPS_CONTROL                  0x19
-#define   TGL_PCODE_TCCOLD                     0x26
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED   REG_BIT(0)
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ     0
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ   REG_BIT(0)
-            /* See also IPS_CTL */
-#define     IPS_PCODE_CONTROL                  (1 << 30)
-#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
-#define   GEN9_PCODE_SAGV_CONTROL              0x21
-#define     GEN9_SAGV_DISABLE                  0x0
-#define     GEN9_SAGV_IS_DISABLED              0x1
-#define     GEN9_SAGV_ENABLE                   0x3
-#define   DG1_PCODE_STATUS                     0x7E
-#define     DG1_UNCORE_GET_INIT_STATUS         0x0
-#define     DG1_UNCORE_INIT_STATUS_COMPLETE    0x1
-#define   PCODE_POWER_SETUP                    0x7C
-#define     POWER_SETUP_SUBCOMMAND_READ_I1     0x4
-#define     POWER_SETUP_SUBCOMMAND_WRITE_I1    0x5
-#define            POWER_SETUP_I1_WATTS                REG_BIT(31)
-#define            POWER_SETUP_I1_SHIFT                6       /* 10.6 fixed point format */
-#define            POWER_SETUP_I1_DATA_MASK            REG_GENMASK(15, 0)
-#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE   0x6
-#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US    0x23
-#define   XEHP_PCODE_FREQUENCY_CONFIG          0x6e    /* pvc */
-/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
-#define     PCODE_MBOX_FC_SC_READ_FUSED_P0     0x0
-#define     PCODE_MBOX_FC_SC_READ_FUSED_PN     0x1
-/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
-/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
-#define     PCODE_MBOX_DOMAIN_NONE             0x0
-#define     PCODE_MBOX_DOMAIN_MEDIAFF          0x3
 #define GEN6_PCODE_DATA                                _MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT       8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT     16

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index c0154fd77fc9ac5499819080c198197b82468437..8cfe9b56f1d095d032589a7e09446b9e12c527c6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -3,6 +3,8 @@
  * Copyright © 2020 Intel Corporation
  */
 
+#include <drm/intel/intel_pcode_regs.h>
+
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"
 #include "display/i9xx_wm_regs.h"

diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index 76c5916b28f451d9d274a3fb25b47a8d099b6d76..c07d48fc1b35502c0a62bc73df077cd2eff56595 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_print.h>
 #include <drm/intel/display_parent_interface.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_drv.h"
 #include "i915_reg.h"

diff --git a/include/drm/intel/intel_pcode_regs.h b/include/drm/intel/intel_pcode_regs.h
new file mode 100644 (file)
index 0000000..db989ee
--- /dev/null
+++ b/include/drm/intel/intel_pcode_regs.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_PCODE_REGS_H_
+#define _INTEL_PCODE_REGS_H_
+
+#define GEN6_PCODE_MAILBOX                     _MMIO(0x138124)
+#define   GEN6_PCODE_READY                     (1 << 31)
+#define   GEN6_PCODE_MB_PARAM2                 REG_GENMASK(23, 16)
+#define   GEN6_PCODE_MB_PARAM1                 REG_GENMASK(15, 8)
+#define   GEN6_PCODE_MB_COMMAND                        REG_GENMASK(7, 0)
+#define   GEN6_PCODE_ERROR_MASK                        0xFF
+#define     GEN6_PCODE_SUCCESS                 0x0
+#define     GEN6_PCODE_ILLEGAL_CMD             0x1
+#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
+#define     GEN6_PCODE_TIMEOUT                 0x3
+#define     GEN6_PCODE_UNIMPLEMENTED_CMD       0xFF
+#define     GEN7_PCODE_TIMEOUT                 0x2
+#define     GEN7_PCODE_ILLEGAL_DATA            0x3
+#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND     0x4
+#define     GEN11_PCODE_LOCKED                 0x6
+#define     GEN11_PCODE_REJECTED               0x11
+#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
+#define   GEN6_PCODE_WRITE_RC6VIDS             0x4
+#define   GEN6_PCODE_READ_RC6VIDS              0x5
+#define     GEN6_ENCODE_RC6_VID(mv)            (((mv) - 245) / 5)
+#define     GEN6_DECODE_RC6_VID(vids)          (((vids) * 5) + 245)
+#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ    0x18
+#define   GEN9_PCODE_READ_MEM_LATENCY          0x6
+#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK    REG_GENMASK(31, 24)
+#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK    REG_GENMASK(23, 16)
+#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK    REG_GENMASK(15, 8)
+#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK    REG_GENMASK(7, 0)
+#define   SKL_PCODE_LOAD_HDCP_KEYS             0x5
+#define   SKL_PCODE_CDCLK_CONTROL              0x7
+#define     SKL_CDCLK_PREPARE_FOR_CHANGE       0x3
+#define     SKL_CDCLK_READY_FOR_CHANGE         0x1
+#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE      0x8
+#define   GEN6_PCODE_READ_MIN_FREQ_TABLE       0x9
+#define   GEN6_READ_OC_PARAMS                  0xc
+#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO       0xd
+#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO  (0x0 << 8)
+#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)        (((point) << 16) | (0x1 << 8))
+#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO  ((0) | (0x2 << 8))
+#define   DISPLAY_TO_PCODE_CDCLK_MAX           0x28D
+#define   DISPLAY_TO_PCODE_VOLTAGE_MASK                REG_GENMASK(1, 0)
+#define          DISPLAY_TO_PCODE_VOLTAGE_MAX          DISPLAY_TO_PCODE_VOLTAGE_MASK
+#define   DISPLAY_TO_PCODE_CDCLK_VALID         REG_BIT(27)
+#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID    REG_BIT(31)
+#define   DISPLAY_TO_PCODE_CDCLK_MASK          REG_GENMASK(25, 16)
+#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK     REG_GENMASK(30, 28)
+#define   DISPLAY_TO_PCODE_CDCLK(x)            REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
+#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)       REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
+#define   DISPLAY_TO_PCODE_VOLTAGE(x)          REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
+#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
+               ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
+               (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
+               (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG      0xe
+#define     ICL_PCODE_REP_QGV_MASK             REG_GENMASK(1, 0)
+#define     ICL_PCODE_REP_QGV_SAFE             REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
+#define     ICL_PCODE_REP_QGV_POLL             REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
+#define     ICL_PCODE_REP_QGV_REJECTED         REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
+#define     ADLS_PCODE_REP_PSF_MASK            REG_GENMASK(3, 2)
+#define     ADLS_PCODE_REP_PSF_SAFE            REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
+#define     ADLS_PCODE_REP_PSF_POLL            REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
+#define     ADLS_PCODE_REP_PSF_REJECTED                REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
+#define     ICL_PCODE_REQ_QGV_PT_MASK          REG_GENMASK(7, 0)
+#define     ICL_PCODE_REQ_QGV_PT(x)            REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
+#define     ADLS_PCODE_REQ_PSF_PT_MASK         REG_GENMASK(10, 8)
+#define     ADLS_PCODE_REQ_PSF_PT(x)           REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
+#define   GEN6_PCODE_READ_D_COMP               0x10
+#define   GEN6_PCODE_WRITE_D_COMP              0x11
+#define   ICL_PCODE_EXIT_TCCOLD                        0x12
+#define   HSW_PCODE_DE_WRITE_FREQ_REQ          0x17
+#define   DISPLAY_IPS_CONTROL                  0x19
+#define   TGL_PCODE_TCCOLD                     0x26
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED   REG_BIT(0)
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ     0
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ   REG_BIT(0)
+/* See also IPS_CTL */
+#define     IPS_PCODE_CONTROL                  (1 << 30)
+#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
+#define   GEN9_PCODE_SAGV_CONTROL              0x21
+#define     GEN9_SAGV_DISABLE                  0x0
+#define     GEN9_SAGV_IS_DISABLED              0x1
+#define     GEN9_SAGV_ENABLE                   0x3
+#define   DG1_PCODE_STATUS                     0x7E
+#define     DG1_UNCORE_GET_INIT_STATUS         0x0
+#define     DG1_UNCORE_INIT_STATUS_COMPLETE    0x1
+#define   PCODE_POWER_SETUP                    0x7C
+#define     POWER_SETUP_SUBCOMMAND_READ_I1     0x4
+#define     POWER_SETUP_SUBCOMMAND_WRITE_I1    0x5
+#define            POWER_SETUP_I1_WATTS                REG_BIT(31)
+#define            POWER_SETUP_I1_SHIFT                6       /* 10.6 fixed point format */
+#define            POWER_SETUP_I1_DATA_MASK            REG_GENMASK(15, 0)
+#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE   0x6
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US    0x23
+#define   XEHP_PCODE_FREQUENCY_CONFIG          0x6e    /* pvc */
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define     PCODE_MBOX_FC_SC_READ_FUSED_P0     0x0
+#define     PCODE_MBOX_FC_SC_READ_FUSED_PN     0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
+#define     PCODE_MBOX_DOMAIN_NONE             0x0
+#define     PCODE_MBOX_DOMAIN_MEDIAFF          0x3
+
+#endif