drm/xe: Define CACHE_MODE_1 as MCR register

CACHE_MODE_1 is a MCR register for all platforms that currently use it
in the Xe driver.  Use XE_REG_MCR() when defining it.

Fixes: 8cd7e9759766 ("drm/xe: Add missing DG2 lrc workarounds")
Fixes: ff063430caa8 ("drm/xe/mtl: Add some initial MTL workarounds")
Bspec: 66534, 67788
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-1-30dd47855fee@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
(cherry picked from commit 8f765f0c054e0fb39980a76b4c899b027395929d)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 9c88ca3ce768d63924f686aaf8f9ca2b3a761408..4399518c270ec10cdb89717d402c50aa991194ae 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -152,7 +152,7 @@
 
 #define XEHPG_INSTDONE_GEOM_SVGUNIT            XE_REG_MCR(0x666c)
 
-#define CACHE_MODE_1                           XE_REG(0x7004, XE_REG_OPTION_MASKED)
+#define CACHE_MODE_1                           XE_REG_MCR(0x7004, XE_REG_OPTION_MASKED)
 #define   MSAA_OPTIMIZATION_REDUC_DISABLE      REG_BIT(11)
 
 #define COMMON_SLICE_CHICKEN1                  XE_REG(0x7010, XE_REG_OPTION_MASKED)