if (!p->ctx)
return -EINVAL;
- if (atomic_read(&p->ctx->guilty)) {
- amdgpu_ctx_put(p->ctx);
- return -ECANCELED;
- }
-
amdgpu_sync_create(&p->sync);
drm_exec_init(&p->exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
DRM_EXEC_IGNORE_DUPLICATES, 0);
}
r = drm_sched_entity_init(&entity->entity, drm_prio, scheds, num_scheds,
- &ctx->guilty);
+ NULL);
if (r)
goto error_free_entity;
#define AMDGPU_RAS_COUNTE_DELAY_MS 3000
+static bool amdgpu_ctx_guilty(struct amdgpu_ctx *ctx)
+{
+ int i, j, r;
+
+ for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
+ for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {
+ struct amdgpu_ctx_entity *ctx_entity;
+
+ ctx_entity = ctx->entities[i][j];
+ if (!ctx_entity)
+ continue;
+
+ r = drm_sched_entity_error(&ctx_entity->entity);
+ if (r == -ETIME)
+ return true;
+ }
+ }
+
+ return false;
+}
+
static int amdgpu_ctx_query2(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv, uint32_t id,
union drm_amdgpu_ctx_out *out)
if (ctx->generation != amdgpu_vm_generation(adev, &fpriv->vm))
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST;
- if (atomic_read(&ctx->guilty))
+ if (amdgpu_ctx_guilty(ctx))
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
if (amdgpu_in_reset(adev))
int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
struct amdgpu_reset_context *reset_context)
{
- int i, r = 0;
struct amdgpu_job *job = NULL;
struct dma_fence *fence = NULL;
struct amdgpu_device *tmp_adev = reset_context->reset_req_dev;
bool need_full_reset =
test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
+ int i, r;
if (reset_context->reset_req_dev == adev)
job = reset_context->job;
amdgpu_fence_driver_isr_toggle(adev, false);
- if (job && job->vm)
- drm_sched_increase_karma(&job->base);
-
r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
if (r == -EOPNOTSUPP)