]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amdgpu: deprecate guilty handling
authorChristian König <christian.koenig@amd.com>
Tue, 5 May 2026 13:40:04 +0000 (15:40 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 4 Jun 2026 19:24:29 +0000 (15:24 -0400)
The guilty handling tried to establish a second way of signaling problems with
the GPU back to userspace. This caused quite a bunch of issue we had to work
around, especially lifetime issues with the drm_sched_entity.

Just drop the handling altogether and use the dma_fence based approach instead.

v2: fix reversed condition in entity check (Alex)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index 32af8cce3df8dc60790bc6f3c815289047f083a2..c42ae3e6fdd13768f0ff269b5032d91e88db6ff0 100644 (file)
@@ -60,11 +60,6 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
        if (!p->ctx)
                return -EINVAL;
 
-       if (atomic_read(&p->ctx->guilty)) {
-               amdgpu_ctx_put(p->ctx);
-               return -ECANCELED;
-       }
-
        amdgpu_sync_create(&p->sync);
        drm_exec_init(&p->exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
                      DRM_EXEC_IGNORE_DUPLICATES, 0);
index 7af86a32c0c5f6cb5436d4ac02194df48bd6ddc3..0d7f6cd74f79be2ea3ad0afcc3aa49a572a5fe34 100644 (file)
@@ -255,7 +255,7 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip,
        }
 
        r = drm_sched_entity_init(&entity->entity, drm_prio, scheds, num_scheds,
-                                 &ctx->guilty);
+                                 NULL);
        if (r)
                goto error_free_entity;
 
@@ -579,6 +579,27 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
 
 #define AMDGPU_RAS_COUNTE_DELAY_MS 3000
 
+static bool amdgpu_ctx_guilty(struct amdgpu_ctx *ctx)
+{
+       int i, j, r;
+
+       for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
+               for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {
+                       struct amdgpu_ctx_entity *ctx_entity;
+
+                       ctx_entity = ctx->entities[i][j];
+                       if (!ctx_entity)
+                               continue;
+
+                       r = drm_sched_entity_error(&ctx_entity->entity);
+                       if (r == -ETIME)
+                               return true;
+               }
+       }
+
+       return false;
+}
+
 static int amdgpu_ctx_query2(struct amdgpu_device *adev,
                             struct amdgpu_fpriv *fpriv, uint32_t id,
                             union drm_amdgpu_ctx_out *out)
@@ -607,7 +628,7 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
        if (ctx->generation != amdgpu_vm_generation(adev, &fpriv->vm))
                out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST;
 
-       if (atomic_read(&ctx->guilty))
+       if (amdgpu_ctx_guilty(ctx))
                out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
 
        if (amdgpu_in_reset(adev))
index cf8d700a22fe80799d1388bc6dc1a4dea6eb7fd6..e444b2088d4005ebaf47c89175e53a889f81e7cf 100644 (file)
@@ -50,7 +50,6 @@ struct amdgpu_ctx {
        int32_t                         init_priority;
        int32_t                         override_priority;
        uint32_t                        stable_pstate;
-       atomic_t                        guilty;
        bool                            preamble_presented;
        uint64_t                        generation;
        unsigned long                   ras_counter_ce;
index f18e465028298aae48d5e31470c45898c80d8836..942f0251c748fa9b62fa38d4232f5ef36bfcac00 100644 (file)
@@ -5112,12 +5112,12 @@ link_reset_failed:
 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
                                 struct amdgpu_reset_context *reset_context)
 {
-       int i, r = 0;
        struct amdgpu_job *job = NULL;
        struct dma_fence *fence = NULL;
        struct amdgpu_device *tmp_adev = reset_context->reset_req_dev;
        bool need_full_reset =
                test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
+       int i, r;
 
        if (reset_context->reset_req_dev == adev)
                job = reset_context->job;
@@ -5143,9 +5143,6 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 
        amdgpu_fence_driver_isr_toggle(adev, false);
 
-       if (job && job->vm)
-               drm_sched_increase_karma(&job->base);
-
        r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
        /* If reset handler not implemented, continue; otherwise return */
        if (r == -EOPNOTSUPP)