intel_de_posting_read(display, regs.imr);
}
-static void error_reset(struct intel_display *display, struct i915_error_regs regs)
+static void error_reset(struct intel_display *display, struct intel_error_regs regs)
{
intel_de_write(display, regs.emr, 0xffffffff);
intel_de_posting_read(display, regs.emr);
intel_de_posting_read(display, regs.eir);
}
-static void error_init(struct intel_display *display, struct i915_error_regs regs,
+static void error_init(struct intel_display *display, struct intel_error_regs regs,
u32 emr_val)
{
intel_de_write(display, regs.eir, 0xffffffff);
#define INTEL_IRQ_REGS(_imr, _ier, _iir) \
((const struct intel_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) })
+struct intel_error_regs {
+ intel_reg_t emr;
+ intel_reg_t eir;
+};
+
+#define INTEL_ERROR_REGS(_emr, _eir) \
+ ((const struct intel_error_regs){ .emr = (_emr), .eir = (_eir) })
+
#define VLV_DISPLAY_BASE 0x180000
/*
#define VLV_ERROR_PAGE_TABLE (1 << 4)
#define VLV_ERROR_CLAIM (1 << 0)
-#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
+#define VLV_ERROR_REGS INTEL_ERROR_REGS(VLV_EMR, VLV_EIR)
#define _MBUS_ABOX0_CTL 0x45038
#define _MBUS_ABOX1_CTL 0x45048