]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
target/i386: add compat for migrating error code
authorFiona Ebner <f.ebner@proxmox.com>
Tue, 10 Mar 2026 15:43:23 +0000 (16:43 +0100)
committerPaolo Bonzini <pbonzini@redhat.com>
Thu, 12 Mar 2026 11:02:55 +0000 (12:02 +0100)
If cpu->env.has_error_code is true, backwards migration of a VM from
a QEMU binary with commit 27535e9cca to a QEMU binary without commit
27535e9cca will fail:

> kvm: error while loading state for instance 0x0 of device 'cpu'

In practice, wrongly setting the error code to 0 on the target is
often unproblematic, so additionally checking error_code != 0 in
cpu_errcode_needed() is not enough to mitigate the issue. Instead, add
proper machine version compat handling.

Cc: qemu-stable@nongnu.org
Fixes: 27535e9cca ("target/i386: Add support for save/load of exception error code")
Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20260310154348.495332-1-f.ebner@proxmox.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
hw/i386/pc.c
target/i386/cpu.c
target/i386/cpu.h
target/i386/machine.c

index addf602da086a8a5f0578ef314cf11ee783e6ca1..4b53b5be4a96047629ff6949a5b66a54300eb734 100644 (file)
@@ -78,6 +78,7 @@ const size_t pc_compat_10_2_len = G_N_ELEMENTS(pc_compat_10_2);
 
 GlobalProperty pc_compat_10_1[] = {
     { "mch", "extended-tseg-mbytes", "16" },
+    { TYPE_X86_CPU, "x-migrate-error-code", "false" },
 };
 const size_t pc_compat_10_1_len = G_N_ELEMENTS(pc_compat_10_1);
 
index 1debc0c61fc54afa6f5f54faea10d3ab173db19f..5b9ae79f165712a882fb2de61355bcb041fb2bf7 100644 (file)
@@ -10651,6 +10651,7 @@ static const Property x86_cpu_properties[] = {
     DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
     DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
                      true),
+    DEFINE_PROP_BOOL("x-migrate-error-code", X86CPU, migrate_error_code, true),
     /*
      * lecacy_cache defaults to true unless the CPU model provides its
      * own cache information (see x86_cpu_load_def()).
index 7bd38f0c0398b4a5d3107a32ed058365292e9e1e..0b539155c4099a46e73b165e4ab3536344dd48ae 100644 (file)
@@ -2361,6 +2361,7 @@ struct ArchCPU {
     bool expose_tcg;
     bool migratable;
     bool migrate_smi_count;
+    bool migrate_error_code;
     uint32_t apic_id;
 
     /* Enables publishing of TSC increment and Local APIC bus frequencies to
index c9139612813b700528cc9ef6b999a2eb98e19149..48a2a4b319077406a0082056977881e8864ffe23 100644 (file)
@@ -466,7 +466,7 @@ static bool cpu_errcode_needed(void *opaque)
 {
     X86CPU *cpu = opaque;
 
-    return cpu->env.has_error_code != 0;
+    return cpu->env.has_error_code != 0 && cpu->migrate_error_code;
 }
 
 static const VMStateDescription vmstate_error_code = {