soc: xilinx: zynqmp: Add TCG variant detection for ZU3TCG

The XCZU3TCG device shares IDCODE 0x04718093 with XCZU3TEG but has
the GPU disable eFuse bit set (Consumer Grade, no GPU). Previously,
the TEG detection branch appended "teg" unconditionally, causing
U-Boot to report the device as zu3teg and failing bitstream ID
checks for xczu3tcg bitstreams.

Check EFUSE_GPU_DIS_MASK in the TEG branch to distinguish the two
sub-variants, mirroring the existing EG/CG detection logic:
- GPU disabled -> TCG family -> "zu3tcg"
- GPU enabled  -> TEG family -> "zu3teg"

Fixes: fa2f0c97af96 ("soc: zynqmp: Add the IDcode for TEG variant")
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/20260623150943.2662500-1-padmarao.begari@amd.com

diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index 4abc73013eb14b72b25c8318981de81acbb01ee5..0e13e230914e544df3ed63a46b11033981a9eea5 100644 (file)
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -358,7 +358,9 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode,
        } else if (device->variants & ZYNQMP_VARIANT_DR_SE) {
                strlcat(priv->machine, "dr_SE", sizeof(priv->machine));
        } else if (device->variants & ZYNQMP_VARIANT_TEG) {
-               strlcat(priv->machine, "teg", sizeof(priv->machine));
+               /* Devices with TEG variant might be TEG or TCG family */
+               strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
+                       "tcg" : "teg", sizeof(priv->machine));
        }
 
        return 0;