]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
x86/msr: Switch wrmsrl() users to wrmsrq()
authorJuergen Gross <jgross@suse.com>
Mon, 8 Jun 2026 08:28:08 +0000 (10:28 +0200)
committerIngo Molnar <mingo@kernel.org>
Mon, 8 Jun 2026 11:16:35 +0000 (13:16 +0200)
wrmsrl() is a deprecated synonym for wrmsrq(). Switch its users to
wrmsrq().

Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "K. Y. Srinivasan" <kys@microsoft.com>
Cc: Haiyang Zhang <haiyangz@microsoft.com>
Cc: Wei Liu <wei.liu@kernel.org>
Cc: Dexuan Cui <decui@microsoft.com>
Cc: Long Li <longli@microsoft.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Link: https://patch.msgid.link/20260608082809.3492719-4-jgross@suse.com
arch/x86/events/amd/uncore.c
arch/x86/events/intel/core.c
arch/x86/kernel/cpu/resctrl/monitor.c
arch/x86/kernel/process_64.c
arch/x86/kvm/pmu.c
arch/x86/kvm/vmx/tdx.c
drivers/hv/mshv_vtl_main.c
drivers/idle/intel_idle.c

index 98ef4bf9911a7327eb4765f08e972db6da3416db..7dc6af4231cca1a18a57af8eec9b38603b2aae5f 100644 (file)
@@ -975,7 +975,7 @@ static void amd_uncore_umc_read(struct perf_event *event)
         * that the counter never gets a chance to saturate.
         */
        if (new & BIT_ULL(63 - COUNTER_SHIFT)) {
-               wrmsrl(hwc->event_base, 0);
+               wrmsrq(hwc->event_base, 0);
                local64_set(&hwc->prev_count, 0);
        } else {
                local64_set(&hwc->prev_count, new);
index dd1e3aa75ee9b739fe2b61a24134c2ed35e65440..e9baa64dc9625b9a6e7a51bbe59db8ab40734b1e 100644 (file)
@@ -3166,12 +3166,12 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
        }
 
        if (cpuc->acr_cfg_b[idx] != mask) {
-               wrmsrl(msr_b + msr_offset, mask);
+               wrmsrq(msr_b + msr_offset, mask);
                cpuc->acr_cfg_b[idx] = mask;
        }
        /* Only need to update the reload value when there is a valid config value. */
        if (mask && cpuc->acr_cfg_c[idx] != reload) {
-               wrmsrl(msr_c + msr_offset, reload);
+               wrmsrq(msr_c + msr_offset, reload);
                cpuc->acr_cfg_c[idx] = reload;
        }
 }
index 4dc112d51d2a545075dfc8c71477ca044d0c19a2..430ae38bab475a331715fdf283343a47879e6775 100644 (file)
@@ -527,7 +527,7 @@ static void resctrl_abmc_config_one_amd(void *info)
 {
        union l3_qos_abmc_cfg *abmc_cfg = info;
 
-       wrmsrl(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full);
+       wrmsrq(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full);
 }
 
 /*
index b85e715ebb305e7b8711cb8befb40d2a9672391b..d44afbe005bb512a8d1ad8a904c112559ff8596b 100644 (file)
@@ -708,7 +708,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
 
        /* Reset hw history on AMD CPUs */
        if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS))
-               wrmsrl(MSR_AMD_WORKLOAD_HRST, 0x1);
+               wrmsrq(MSR_AMD_WORKLOAD_HRST, 0x1);
 
        return prev_p;
 }
index e218352e342311e32b4570fa8fcf8666fb3d5eae..aee70e5dc15d94c2b6f5210f95279aa0e13ee49d 100644 (file)
@@ -1313,14 +1313,14 @@ static void kvm_pmu_load_guest_pmcs(struct kvm_vcpu *vcpu)
                pmc = &pmu->gp_counters[i];
 
                if (pmc->counter != rdpmc(i))
-                       wrmsrl(gp_counter_msr(i), pmc->counter);
-               wrmsrl(gp_eventsel_msr(i), pmc->eventsel_hw);
+                       wrmsrq(gp_counter_msr(i), pmc->counter);
+               wrmsrq(gp_eventsel_msr(i), pmc->eventsel_hw);
        }
        for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
                pmc = &pmu->fixed_counters[i];
 
                if (pmc->counter != rdpmc(INTEL_PMC_FIXED_RDPMC_BASE | i))
-                       wrmsrl(fixed_counter_msr(i), pmc->counter);
+                       wrmsrq(fixed_counter_msr(i), pmc->counter);
        }
 }
 
index 04ce321ebdf396848b464e306b86292d0a740db0..cb50e23c39cab4202975db146e10d7e434144598 100644 (file)
@@ -823,7 +823,7 @@ static void tdx_prepare_switch_to_host(struct kvm_vcpu *vcpu)
                return;
 
        ++vcpu->stat.host_state_reload;
-       wrmsrl(MSR_KERNEL_GS_BASE, vt->msr_host_kernel_gs_base);
+       wrmsrq(MSR_KERNEL_GS_BASE, vt->msr_host_kernel_gs_base);
 
        vt->guest_state_loaded = false;
 }
@@ -1048,10 +1048,10 @@ static void tdx_load_host_xsave_state(struct kvm_vcpu *vcpu)
 
        /*
         * Likewise, even if a TDX hosts didn't support XSS both arms of
-        * the comparison would be 0 and the wrmsrl would be skipped.
+        * the comparison would be 0 and the wrmsrq would be skipped.
         */
        if (kvm_host.xss != (kvm_tdx->xfam & kvm_caps.supported_xss))
-               wrmsrl(MSR_IA32_XSS, kvm_host.xss);
+               wrmsrq(MSR_IA32_XSS, kvm_host.xss);
 }
 
 #define TDX_DEBUGCTL_PRESERVED (DEBUGCTLMSR_BTF | \
index f5d27f28d6ad971cf6a632180f4ef98a88e75017..0d3d4161974f8ba4a72724f35f8892c43f909a10 100644 (file)
@@ -596,7 +596,7 @@ static int mshv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set)
                } else {
                        /* Handle MSRs */
                        if (set)
-                               wrmsrl(reg_table[i].msr_addr, *reg64);
+                               wrmsrq(reg_table[i].msr_addr, *reg64);
                        else
                                rdmsrq(reg_table[i].msr_addr, *reg64);
                }
index 15c698291b32a8b147e3690a4f1127ed32934b39..67d5993c73875a1de377083889599ac7053cf352 100644 (file)
@@ -2379,7 +2379,7 @@ static void intel_c1_demotion_toggle(void *enable)
                msr_val |= NHM_C1_AUTO_DEMOTE | SNB_C1_AUTO_UNDEMOTE;
        else
                msr_val &= ~(NHM_C1_AUTO_DEMOTE | SNB_C1_AUTO_UNDEMOTE);
-       wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
+       wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
 }
 
 static ssize_t intel_c1_demotion_store(struct device *dev,