]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/ast: Gen4: Fix open-coded register access
authorThomas Zimmermann <tzimmermann@suse.de>
Fri, 27 Mar 2026 13:33:04 +0000 (14:33 +0100)
committerThomas Zimmermann <tzimmermann@suse.de>
Wed, 8 Apr 2026 09:04:49 +0000 (11:04 +0200)
Replace all open-coded access to MCR and SCU registers in Gen4 with the
appropriate calls to ast_moutdwm() and ast_mindwm(). Use MCR and SCU
register constants. Name variables according to registers.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patch.msgid.link/20260327133532.79696-13-tzimmermann@suse.de
drivers/gpu/drm/ast/ast_2300.c
drivers/gpu/drm/ast/ast_reg.h

index 96d9909d942c4bd2c56ab6fee9c20d3e32397ef5..cbeac6990c27291c179add5da3a09f465103ff76 100644 (file)
@@ -1245,22 +1245,15 @@ static void ast_post_chip_2300(struct ast_device *ast)
 
        reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
        if ((reg & 0x80) == 0) {/* vga only */
-               ast_write32(ast, 0xf004, AST_REG_MCR00);
-               ast_write32(ast, 0xf000, 0x1);
-               ast_write32(ast, 0x12000, 0x1688a8a8);
-               do {
-                       ;
-               } while (ast_read32(ast, 0x12000) != 0x1);
+               u32 scu008, scu040;
 
-               ast_write32(ast, 0x10000, 0xfc600309);
-               do {
-                       ;
-               } while (ast_read32(ast, 0x10000) != 0x1);
+               ast_moutdwm_poll(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY, 0x01);
+               ast_moutdwm_poll(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY, 0x01);
 
                /* Slow down CPU/AHB CLK in VGA only mode */
-               temp = ast_read32(ast, 0x12008);
-               temp |= 0x73;
-               ast_write32(ast, 0x12008, temp);
+               scu008 = ast_mindwm(ast, AST_REG_SCU008);
+               scu008 |= 0x00000073;
+               ast_moutdwm(ast, AST_REG_SCU008, scu008);
 
                param.dram_freq = 396;
                param.dram_type = AST_DDR3;
@@ -1306,8 +1299,9 @@ static void ast_post_chip_2300(struct ast_device *ast)
                        ddr2_init(ast, &param);
                }
 
-               temp = ast_mindwm(ast, AST_REG_SCU040);
-               ast_moutdwm(ast, AST_REG_SCU040, temp | 0x40);
+               scu040 = ast_mindwm(ast, AST_REG_SCU040);
+               scu040 |= 0x00000040;
+               ast_moutdwm(ast, AST_REG_SCU040, scu040);
        }
 
        /* wait ready */
index 9ebdbbde9a47d1ab5ddaee13a82376740c2fa6a8..c3473cad454504b585ae350806875c76c737a9ce 100644 (file)
 #define AST_REG_SCU(__offset)                  (AST_REG_SCU_BASE + (__offset))
 #define AST_REG_SCU000                         AST_REG_SCU(0x000)
 #define AST_REG_SCU000_PROTECTION_KEY          (0x1688a8a8)
+#define AST_REG_SCU008                         AST_REG_SCU(0x008)
 #define AST_REG_SCU00C                         AST_REG_SCU(0x00c)
 #define AST_REG_SCU020                         AST_REG_SCU(0x020)
 #define AST_REG_SCU040                         AST_REG_SCU(0x040)