rs6000: Emit insn with proper rounding mode for nearbyint

This patch emits instruction with proper rounding mode for
vec_nearbyint.Previously, xvrdpi was emitted which uses nearest away
rounding mode but nearbyint requires rounding mode to be current
rounding mode.

Bootstrapped and regtested on powerpc64le-linux-gnu with no regressions.

2026-05-08  Vijay Shankar  <vijay@linux.ibm.com>

gcc/ChangeLog:
	PR target/113353
	* config/rs6000/rs6000.cc (rs6000_builtin_vectorized_function):
	Emit xvrdpic/xvrspic.
	* config/rs6000/rs6000-overload.def (__builtin_vec_nearbyint):
	Modified bif-id and overload-id.

gcc/testsuite/ChangeLog:
	PR target/113353
	* gcc.target/powerpc/vsx-vector-1.c: Fix testcase.
	* gcc.target/powerpc/vsx-vector-2.c: Fix testcase.
	* gcc.target/powerpc/vsx-vector-6-func-1op.c: Fix testcase.

diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 5238c81b2144004ebc522e8d01599dbb791807b4..ef7b59ed112a4a4670dc5f79fffd823fb9a6f535 100644 (file)
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -2644,9 +2644,9 @@
 
 [VEC_NEARBYINT, vec_nearbyint, __builtin_vec_nearbyint]
   vf __builtin_vec_nearbyint (vf);
-    XVRSPI  XVRSPI_NBI
+    XVRSPIC XVRSPIC_NBI
   vd __builtin_vec_nearbyint (vd);
-    XVRDPI  XVRDPI_NBI
+    XVRDPIC XVRDPIC_NBI
 
 [VEC_NEG, vec_neg, __builtin_vec_neg]
   vsc __builtin_vec_neg (vsc);

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7d61001cb3497d0278bed0e5b71bdb3f6dcd6789..fba481b2b5def786c2dbab9135bb4e335146655e 100644 (file)
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5696,12 +5696,12 @@ rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
          && flag_unsafe_math_optimizations
          && out_mode == DFmode && out_n == 2
          && in_mode == DFmode && in_n == 2)
-       return rs6000_builtin_decls[RS6000_BIF_XVRDPI];
+       return rs6000_builtin_decls[RS6000_BIF_XVRDPIC];
       if (VECTOR_UNIT_VSX_P (V4SFmode)
          && flag_unsafe_math_optimizations
          && out_mode == SFmode && out_n == 4
          && in_mode == SFmode && in_n == 4)
-       return rs6000_builtin_decls[RS6000_BIF_XVRSPI];
+       return rs6000_builtin_decls[RS6000_BIF_XVRSPIC];
       break;
     CASE_CFN_RINT:
       if (VECTOR_UNIT_VSX_P (V2DFmode)

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
index 4d705e46d9a98e47eab4427f5f6fd902ed7a63f4..a9391c5475dba40f73a2e70de0b97d545da99c2b 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
@@ -14,7 +14,7 @@
 /* { dg-final { scan-assembler "xvrdpip" } } */
 /* { dg-final { scan-assembler "xvrdpiz" } } */
 /* { dg-final { scan-assembler "xvrdpic" } } */
-/* { dg-final { scan-assembler "xvrdpi " } } */
+/* { dg-final { scan-assembler-not {\mxvrdpi\M} } } */
 
 #ifndef SIZE
 #define SIZE 1024

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
index a0fe088bbfd1cc553325cd16c506d9c7fd9bca2a..061e4ae8be104d66353a28c07627fcb2cfa50c1b 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
@@ -14,7 +14,7 @@
 /* { dg-final { scan-assembler "xvrspip" } } */
 /* { dg-final { scan-assembler "xvrspiz" } } */
 /* { dg-final { scan-assembler "xvrspic" } } */
-/* { dg-final { scan-assembler "xvrspi " } } */
+/* { dg-final { scan-assembler-not {\mxvrspi\M} } } */
 
 #ifndef SIZE
 #define SIZE 1024

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c
index 6d2c64b248a012382800875372d35361b1663d66..6f629c47155ba254952d26ef8eb7e8e38c6cd42b 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.c
@@ -10,13 +10,11 @@
 /* { dg-final { scan-assembler-times {\mxvabssp\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mxvrspip\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mxvrspim\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrspi\M} 1 } } */ 
-/* { dg-final { scan-assembler-times {\mxvrspic\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrspic\M} 2 } } */
 /* { dg-final { scan-assembler-times {\mxvrspiz\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mxvrdpip\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mxvrdpim\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrdpic\M} 2 } } */
 /* { dg-final { scan-assembler-times {\mxvrdpiz\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 1 } } */