clk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting

The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: e700bfd2f976 ("clk: qcom: Add support for Display clock Controllers on SA8775P")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-5-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/dispcc0-sa8775p.c b/drivers/clk/qcom/dispcc0-sa8775p.c
index aeda9cf4bfee8934659a8a5440d48f52b6f69fdb..b248fa970587351667f2800624d0117cabc0c6b0 100644 (file)
--- a/drivers/clk/qcom/dispcc0-sa8775p.c
+++ b/drivers/clk/qcom/dispcc0-sa8775p.c
@@ -591,7 +591,6 @@ static struct clk_regmap_div mdss_0_disp_cc_mdss_byte0_div_clk_src = {
                        &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };
@@ -606,7 +605,6 @@ static struct clk_regmap_div mdss_0_disp_cc_mdss_byte1_div_clk_src = {
                        &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };

diff --git a/drivers/clk/qcom/dispcc1-sa8775p.c b/drivers/clk/qcom/dispcc1-sa8775p.c
index cd55d1c11902417eb78e3507d757b20382e8bab5..9882edbb79f9e384ef215cf6955b7bd83ce45ec3 100644 (file)
--- a/drivers/clk/qcom/dispcc1-sa8775p.c
+++ b/drivers/clk/qcom/dispcc1-sa8775p.c
@@ -591,7 +591,6 @@ static struct clk_regmap_div mdss_1_disp_cc_mdss_byte0_div_clk_src = {
                        &mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };
@@ -606,7 +605,6 @@ static struct clk_regmap_div mdss_1_disp_cc_mdss_byte1_div_clk_src = {
                        &mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };