}
}
+static void i5100_set_error_reporting(struct pci_dev *pdev, bool enable)
+{
+ u32 dw;
+
+ pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
+
+ /* Enable with 0, disable with 1 */
+ if (enable)
+ dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
+ else
+ dw |= I5100_FERR_NF_MEM_ANY_MASK;
+
+ pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
+}
+
/****************************************************************************
* Error injection routines
****************************************************************************/
pci_read_config_dword(pdev, I5100_MS, &dw);
ranksperch = !!(dw & (1 << 8)) * 2 + 4;
- /* enable error reporting... */
- pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
- dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
- pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
-
/* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_5100_21, 0);
i5100_setup_debugfs(mci);
+ /* Enable error reporting on success */
+ i5100_set_error_reporting(pdev, true);
+
return ret;
bail_scrub:
priv = mci->pvt_info;
+ /* Disable error reporting at teardown */
+ i5100_set_error_reporting(pdev, false);
+
edac_debugfs_remove_recursive(priv->debugfs);
priv->scrub_enable = 0;