return cpu;
}
+/* Get the specific type of HYGON CPU and return HYGON CPU name. Return
+ NULL for unknown HYGON CPU. */
+
+static inline const char *
+get_hygon_cpu (struct __processor_model *cpu_model,
+ struct __processor_model2 *cpu_model2,
+ unsigned int *cpu_features2 __attribute__((unused)))
+{
+ const char *cpu = NULL;
+ unsigned int family = cpu_model2->__cpu_family;
+ unsigned int model = cpu_model2->__cpu_model;
+
+ switch (family)
+ {
+ case 0x18:
+ cpu_model->__cpu_type = HYGONFAM18H;
+ if (model == 0x4)
+ {
+ cpu = "c86-4g-m4";
+ CHECK___builtin_cpu_is ("c86-4g-m4");
+ cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M4;
+ }
+ else if (model == 0x6)
+ {
+ cpu = "c86-4g-m6";
+ CHECK___builtin_cpu_is ("c86-4g-m6");
+ cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M6;
+ }
+ else if (model == 0x7)
+ {
+ cpu = "c86-4g-m7";
+ CHECK___builtin_cpu_is ("c86-4g-m7");
+ cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M7;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return cpu;
+}
+
/* Get the specific type of Intel CPU and return Intel CPU name. Return
NULL for unknown Intel CPU. */
cpu_model->__cpu_vendor = VENDOR_CYRIX;
else if (vendor == signature_NSC_ebx)
cpu_model->__cpu_vendor = VENDOR_NSC;
+ else if (vendor == signature_HYGON_ebx)
+ {
+ /* Adjust model and family for HYGON CPUS. */
+ if (family == 0x0f)
+ {
+ family += extended_family;
+ model += extended_model;
+ }
+ cpu_model2->__cpu_family = family;
+ cpu_model2->__cpu_model = model;
+
+ /* Get CPU type. */
+ get_hygon_cpu (cpu_model, cpu_model2, cpu_features2);
+ cpu_model->__cpu_vendor = VENDOR_HYGON;
+ }
else
cpu_model->__cpu_vendor = VENDOR_OTHER;
"znver3",
"znver4",
"znver5",
- "znver6"
+ "znver6",
+ "c86-4g-m4",
+ "c86-4g-m6",
+ "c86-4g-m7"
};
/* Guarantee that the array is aligned with enum processor_type. */
{"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
PTA_BTVER2,
M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
+ {"c86-4g-m4", PROCESSOR_C86_4G_M4, CPU_C86_4G_M4,
+ PTA_C86_4G_M4,
+ M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M4), P_PROC_AVX2},
+ {"c86-4g-m6", PROCESSOR_C86_4G_M6, CPU_C86_4G_M6,
+ PTA_C86_4G_M6,
+ M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M6), P_PROC_AVX2},
+ {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,
+ PTA_C86_4G_M7,
+ M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},
{"generic", PROCESSOR_GENERIC, CPU_GENERIC,
PTA_64BIT
M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
{"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
+ {"hygon", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_VENDOR (VENDOR_HYGON), P_NONE},
+ {"hygonfam18h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (HYGONFAM18H), P_NONE},
};
/* NB: processor_alias_table stops at the "generic" entry. */
-unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7;
+unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 9;
unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
/* Provide valid option values for -march and -mtune options. */
VENDOR_INTEL = 1,
VENDOR_AMD,
VENDOR_ZHAOXIN,
+ VENDOR_HYGON,
VENDOR_OTHER,
VENDOR_CENTAUR,
VENDOR_CYRIX,
INTEL_GRANDRIDGE,
INTEL_CLEARWATERFOREST,
AMDFAM1AH,
+ HYGONFAM18H,
CPU_TYPE_MAX,
BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX
};
INTEL_COREI7_DIAMONDRAPIDS,
INTEL_COREI7_NOVALAKE,
AMDFAM1AH_ZNVER6,
+ HYGONFAM18H_C86_4G_M4,
+ HYGONFAM18H_C86_4G_M6,
+ HYGONFAM18H_C86_4G_M7,
CPU_SUBTYPE_MAX
};
nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \
arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids novalake \
-native"
+c86-4g-m4 c86-4g-m6 c86-4g-m7 native"
# Additional x86 processors supported by --with-cpu=. Each processor
# MUST be separated by exactly one space.
cpu=pentiumpro
arch_without_sse2=yes
;;
+ c86_4g_m4-*)
+ arch=c86-4g-m4
+ cpu=c86-4g-m4
+ ;;
+ c86_4g_m6-*)
+ arch=c86-4g-m6
+ cpu=c86-4g-m6
+ ;;
+ c86_4g_m7-*)
+ arch=c86-4g-m7
+ cpu=c86-4g-m7
+ ;;
*)
arch=pentiumpro
cpu=generic
arch=corei7
cpu=corei7
;;
+ c86_4g_m4-*)
+ arch=c86-4g-m4
+ cpu=c86-4g-m4
+ ;;
+ c86_4g_m6-*)
+ arch=c86-4g-m6
+ cpu=c86-4g-m6
+ ;;
+ c86_4g_m7-*)
+ arch=c86-4g-m7
+ cpu=c86-4g-m7
+ ;;
*)
arch=x86-64
cpu=generic
--- /dev/null
+;; Copyright (C) 2026 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+;;
+
+;; HYGON c86-4g-m7 Scheduling
+;; Modeling automatons for decoders, integer execution pipes,
+;; AGU pipes, branch, floating point execution and fp store units.
+(define_automaton "c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu")
+
+;; Decoders unit has 4 decoders and all of them can decode fast path
+;; and vector type instructions.
+(define_cpu_unit "c86-4g-m7-decode0" "c86_4g_m7")
+(define_cpu_unit "c86-4g-m7-decode1" "c86_4g_m7")
+(define_cpu_unit "c86-4g-m7-decode2" "c86_4g_m7")
+(define_cpu_unit "c86-4g-m7-decode3" "c86_4g_m7")
+
+;; Currently blocking all decoders for vector path instructions as
+;; they are dispatched separetely as microcode sequence.
+(define_reservation "c86-4g-m7-vector" "c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3")
+
+;; Direct instructions can be issued to any of the four decoders.
+(define_reservation "c86-4g-m7-direct" "c86-4g-m7-decode0|c86-4g-m7-decode1|c86-4g-m7-decode2|c86-4g-m7-decode3")
+
+;; Fix me: Need to revisit this later to simulate fast path double behavior.
+(define_reservation "c86-4g-m7-double" "c86-4g-m7-direct")
+
+;; Integer unit 4 ALU pipes.
+(define_cpu_unit "c86-4g-m7-ieu0" "c86_4g_m7_ieu")
+(define_cpu_unit "c86-4g-m7-ieu1" "c86_4g_m7_ieu")
+(define_cpu_unit "c86-4g-m7-ieu2" "c86_4g_m7_ieu")
+(define_cpu_unit "c86-4g-m7-ieu3" "c86_4g_m7_ieu")
+
+;; c86-4g-m7 has an additional branch unit.
+(define_cpu_unit "c86-4g-m7-bru0" "c86_4g_m7_ieu")
+(define_reservation "c86-4g-m7-ieu" "c86-4g-m7-ieu0|c86-4g-m7-ieu1|c86-4g-m7-ieu2|c86-4g-m7-ieu3")
+
+;; 3 AGU pipes in c86-4g-m7
+(define_cpu_unit "c86-4g-m7-agu0" "c86_4g_m7_agu")
+(define_cpu_unit "c86-4g-m7-agu1" "c86_4g_m7_agu")
+(define_cpu_unit "c86-4g-m7-agu2" "c86_4g_m7_agu")
+(define_reservation "c86-4g-m7-agu-reserve" "c86-4g-m7-agu0|c86-4g-m7-agu1|c86-4g-m7-agu2")
+
+;; Load is 4 cycles. We do not model reservation of load unit.
+(define_reservation "c86-4g-m7-load" "c86-4g-m7-agu-reserve")
+(define_reservation "c86-4g-m7-store" "c86-4g-m7-agu-reserve")
+
+;; vectorpath (microcoded) instructions are single issue instructions.
+;; So, they occupy all the integer units.
+(define_reservation "c86-4g-m7-ivector" "c86-4g-m7-ieu0+c86-4g-m7-ieu1
+ +c86-4g-m7-ieu2+c86-4g-m7-ieu3+c86-4g-m7-bru0
+ +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
+
+;; Floating point unit 4 FP pipes.
+(define_cpu_unit "c86-4g-m7-fpu0" "c86_4g_m7_fpu")
+(define_cpu_unit "c86-4g-m7-fpu1" "c86_4g_m7_fpu")
+(define_cpu_unit "c86-4g-m7-fpu2" "c86_4g_m7_fpu")
+(define_cpu_unit "c86-4g-m7-fpu3" "c86_4g_m7_fpu")
+(define_reservation "c86-4g-m7-fpu" "c86-4g-m7-fpu0|c86-4g-m7-fpu1|c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+(define_reservation "c86-4g-m7-fpu_0_2" "c86-4g-m7-fpu0|c86-4g-m7-fpu2")
+(define_reservation "c86-4g-m7-fpu_1_3" "c86-4g-m7-fpu1|c86-4g-m7-fpu3")
+(define_reservation "c86-4g-m7-fpu_0_1" "c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+(define_reservation "c86-4g-m7-fpu_0_2x2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu2*2")
+(define_reservation "c86-4g-m7-fpu_0_2x4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu2*4")
+(define_reservation "c86-4g-m7-fvector" "c86-4g-m7-fpu0+c86-4g-m7-fpu1
+ +c86-4g-m7-fpu2+c86-4g-m7-fpu3
+ +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
+
+;; IMOV/IMOVX
+(define_insn_reservation "c86_4g_m7_imov_xchg" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "imov")
+ (and (eq_attr "c86_decode" "vector")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct")
+
+(define_insn_reservation "c86_4g_m7_imov_xchg_load" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "imov")
+ (and (eq_attr "c86_decode" "vector")
+ (eq_attr "memory" "!none"))))
+ "c86-4g-m7-direct,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_imovx_cwde" 2
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "imovx")
+ (and (eq_attr "c86_decode" "double")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-ieu")
+
+(define_insn_reservation "c86_4g_m7_imov" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "imov,imovx")
+ (and (eq_attr "c86_decode" "direct")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-ieu")
+
+(define_insn_reservation "c86_4g_m7_imov_load" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "imov,imovx")
+ (and (eq_attr "c86_decode" "!vector")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
+
+(define_insn_reservation "c86_4g_m7_imov_store" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "imov,imovx")
+ (and (eq_attr "c86_decode" "!vector")
+ (eq_attr "memory" "store"))))
+ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu")
+
+;; PUSH
+(define_insn_reservation "c86_4g_m7_push" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "push,sse")
+ (eq_attr "memory" "store")))
+ "c86-4g-m7-direct,c86-4g-m7-store")
+
+(define_insn_reservation "c86_4g_m7_push_mem" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "push")
+ (eq_attr "memory" "both")))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store")
+
+;; POP
+(define_insn_reservation "c86_4g_m7_pop" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "pop")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-direct,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_pop_mem" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "pop")
+ (eq_attr "memory" "both")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store")
+
+;; IMUL/IMULX
+(define_insn_reservation "c86_4g_m7_imul" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "imul,imulx")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-direct,c86-4g-m7-ieu1")
+
+(define_insn_reservation "c86_4g_m7_imul_load" 7
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "imul")
+ (eq_attr "memory" "!none")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu1")
+
+;; IDIV
+(define_insn_reservation "c86_4g_m7_idiv_DI" 41
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "DI")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-double,c86-4g-m7-ieu3*41")
+
+(define_insn_reservation "c86_4g_m7_idiv_SI" 25
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "SI")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-double,c86-4g-m7-ieu3*25")
+
+(define_insn_reservation "c86_4g_m7_idiv_HI" 17
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "HI")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-double,c86-4g-m7-ieu3*17")
+
+(define_insn_reservation "c86_4g_m7_idiv_QI" 15
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "QI")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-ieu3*15")
+
+(define_insn_reservation "c86_4g_m7_idiv_DI_load" 45
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "DI")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*41")
+
+(define_insn_reservation "c86_4g_m7_idiv_SI_load" 29
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "SI")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*25")
+
+(define_insn_reservation "c86_4g_m7_idiv_HI_load" 21
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "HI")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*17")
+
+(define_insn_reservation "c86_4g_m7_idiv_QI_load" 19
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "QI")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu3*15")
+
+;; Integer/genaral Instructions
+(define_insn_reservation "c86_4g_m7_insn" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "alu,negnot,rotate1,ishift1,test,incdec,icmp,
+ rotate,rotatex,ishift,ishiftx,icmov")
+ (eq_attr "memory" "none,unknown")))
+ "c86-4g-m7-direct,c86-4g-m7-ieu")
+
+(define_insn_reservation "c86_4g_m7_insn_load" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "alu,incdec,icmp,test,ishift,
+ ishiftx,icmov,rotate,rotatex")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
+
+(define_insn_reservation "c86_4g_m7_insn_store" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ishift1,rotate1,rotate,incdec,
+ alu,icmov,ishift,negnot,alu1")
+ (eq_attr "memory" "store")))
+ "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
+
+(define_insn_reservation "c86_4g_m7_insn2_store" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "icmp")
+ (eq_attr "memory" "store")))
+ "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
+
+(define_insn_reservation "c86_4g_m7_insn_both" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "alu,negnot,rotate1,ishift1,incdec,rotate,
+ rotatex,ishift,ishiftx,icmov")
+ (eq_attr "memory" "both")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu,c86-4g-m7-store")
+
+(define_insn_reservation "c86_4g_m7_setcc" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "setcc")
+ (eq_attr "memory" "none,unknown")))
+ "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+
+(define_insn_reservation "c86_4g_m7_setcc_load" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "setcc")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+
+(define_insn_reservation "c86_4g_m7_setcc_store" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "setcc")
+ (eq_attr "memory" "store")))
+ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+
+;; ALU1
+(define_insn_reservation "c86_4g_m7_alu1_double" 2
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "alu1")
+ (and (eq_attr "c86_decode" "double")
+ (eq_attr "memory" "none,unknown"))))
+ "c86-4g-m7-double,c86-4g-m7-ieu")
+
+(define_insn_reservation "c86_4g_m7_alu1_double_load" 6
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "alu1")
+ (and (eq_attr "c86_decode" "double")
+ (eq_attr "memory" "both"))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
+
+(define_insn_reservation "c86_4g_m7_alu1_vector" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "alu1")
+ (and (eq_attr "c86_decode" "vector")
+ (eq_attr "memory" "none,unknown"))))
+ "c86-4g-m7-vector,c86-4g-m7-ivector*3")
+
+(define_insn_reservation "c86_4g_m7_alu1_vector_load" 7
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "alu1")
+ (and (eq_attr "c86_decode" "vector")
+ (eq_attr "memory" "both"))))
+ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ivector*3")
+
+(define_insn_reservation "c86_4g_m7_alu1_direct" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "alu1")
+ (and (eq_attr "c86_decode" "direct")
+ (eq_attr "memory" "none,unknown"))))
+ "c86-4g-m7-direct,c86-4g-m7-ieu")
+
+(define_insn_reservation "c86_4g_m7_alu1_direct_load" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "alu1")
+ (and (eq_attr "c86_decode" "direct")
+ (eq_attr "memory" "both"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
+
+;; CALL/CALLV
+(define_insn_reservation "c86_4g_m7_call" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (eq_attr "type" "call,callv"))
+ "c86-4g-m7-double,c86-4g-m7-ieu0|c86-4g-m7-bru0,c86-4g-m7-store")
+
+;; IBR
+(define_insn_reservation "c86_4g_m7_branch" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ibr")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-bru0")
+
+(define_insn_reservation "c86_4g_m7_branch_load" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ibr")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-bru0")
+
+;; LEA
+(define_insn_reservation "c86_4g_m7_lea" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (eq_attr "type" "lea"))
+ "c86-4g-m7-direct,c86-4g-m7-ieu")
+
+;; LEAVE
+(define_insn_reservation "c86_4g_m7_leave" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (eq_attr "type" "leave"))
+ "c86-4g-m7-double,c86-4g-m7-ieu,c86-4g-m7-store")
+
+;; STR
+(define_insn_reservation "c86_4g_m7_str" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "str")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-vector,c86-4g-m7-ivector*3")
+
+(define_insn_reservation "c86_4g_m7_str_load" 7
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "str")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*3")
+
+
+(define_insn_reservation "c86_4g_m7_ieu_vector" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "other,multi")
+ (and (eq_attr "unit" "!i387")
+ (eq_attr "memory" "none,unknown"))))
+ "c86-4g-m7-vector,c86-4g-m7-ivector*5")
+
+(define_insn_reservation "c86_4g_m7_ieu_vector_load" 9
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "other,multi")
+ (and (eq_attr "unit" "!i387")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*5")
+
+;; SSEINS
+(define_insn_reservation "c86_4g_m7_sse_insertimm" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseins")
+ (and (eq_attr "memory" "none")
+ (eq_attr "length_immediate" "2"))))
+ "c86-4g-m7-double,c86-4g-m7-fpu0|c86-4g-m7-fpu3,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_sse_insert" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseins")
+ (and (eq_attr "memory" "none")
+ (eq_attr "length_immediate" "!2"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1")
+
+;; FCMOV
+(define_insn_reservation "c86_4g_m7_fp_cmov" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (eq_attr "type" "fcmov"))
+ "c86-4g-m7-vector,c86-4g-m7-fvector*3")
+
+;; FLD
+(define_insn_reservation "c86_4g_m7_fp_mov_direct_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+
+;; FST
+(define_insn_reservation "c86_4g_m7_fp_mov_direct_store" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "store"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-store")
+
+;; FILD
+(define_insn_reservation "c86_4g_m7_fp_mov_double_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "c86_decode" "double")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+
+;; FIST
+(define_insn_reservation "c86_4g_m7_fp_mov_double_store" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "c86_decode" "double")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "store"))))
+ "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-store")
+
+(define_insn_reservation "c86_4g_m7_fp_mov_direct" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1")
+
+;; FSQRT
+(define_insn_reservation "c86_4g_m7fp_sqrt" 22
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fpspc")
+ (eq_attr "c86_attr" "sqrt")))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1*22")
+
+;; FPSPC
+(define_insn_reservation "c86_4g_m7_fp_spc_direct" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fpspc")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "store")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_fp_spc" 6
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fpspc")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-vector,c86-4g-m7-fvector*6")
+
+(define_insn_reservation "c86_4g_m7_fp_op_mul" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fop,fmul")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_fp_op_mul_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fop,fmul")
+ (and (eq_attr "fp_int_src" "false")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_fp_op_imul_load" 16
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fmul")
+ (and (eq_attr "fp_int_src" "true")
+ (eq_attr "memory" "!none"))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu_0_2")
+
+;; FDIV
+(define_insn_reservation "c86_4g_m7_fp_div" 15
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1*7")
+
+(define_insn_reservation "c86_4g_m7_fp_div_load" 22
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fdiv")
+ (and (eq_attr "fp_int_src" "false")
+ (eq_attr "memory" "!none"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7")
+
+(define_insn_reservation "c86_4g_m7_fp_idiv_load" 26
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fdiv")
+ (and (eq_attr "fp_int_src" "true")
+ (eq_attr "memory" "!none"))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*7")
+
+(define_insn_reservation "c86_4g_m7_fp_fsgn" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (eq_attr "type" "fsgn"))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+
+;; FCMP
+(define_insn_reservation "c86_4g_m7_fp_fcmp" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fcmp")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-double,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_fp_fcmp_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "fcmp")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
+
+;; MMX
+(define_insn_reservation "c86_4g_m7_fp_mmx" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (eq_attr "type" "mmx"))
+ "c86-4g-m7-direct")
+
+(define_insn_reservation "c86_4g_m7_mmx_add_cmp" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxadd,mmxcmp")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-direct,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_mmx_add_cmp_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxadd,mmxcmp")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_mmx_cvt" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxcvt")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_mmx_cvt_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxcvt")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_mmx_shift" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxshft")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_mmx_shift_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxshft")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_mmx_shift_avg" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxshft")
+ (and (eq_attr "c86_attr" "avg")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_mmx_shift_avg_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxshft")
+ (and (eq_attr "c86_attr" "avg")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+
+;; SADBW
+(define_insn_reservation "c86_4g_m7_mmx_shift_sadbw" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxshft")
+ (and (eq_attr "c86_attr" "sadbw")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu0")
+
+(define_insn_reservation "c86_4g_m7_mmx_shift_sadbw_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxshft")
+ (and (eq_attr "c86_attr" "sadbw")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+
+(define_insn_reservation "c86_4g_m7_mmx_mov" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxmov")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_mmx_mov_store" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxmov")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "store"))))
+ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_mmx_mov_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxmov")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_mmx_mul" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxmul")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-direct,c86-4g-m7-fpu0")
+
+(define_insn_reservation "c86_4g_m7_mmx_mul_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mmxmul")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+
+;; PINSR
+(define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,mmxcvt")
+ (and (eq_attr "c86_attr" "insr")
+ (and (eq_attr "prefix" "orig")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-double,c86-4g-m7-ieu2,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,mmxcvt")
+ (and (eq_attr "c86_attr" "insr")
+ (and (eq_attr "prefix" "orig")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_avx_vpinsr_reg" 2
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "insr")
+ (and (eq_attr "prefix" "!orig")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-double,c86-4g-m7-fpu2*2")
+
+(define_insn_reservation "c86_4g_m7_avx_vpinsr_reg_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "insr")
+ (and (eq_attr "prefix" "!orig")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+
+;; PERM
+(define_insn_reservation "c86_4g_m7_avx512_perm_xmm" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (ior (and (eq_attr "c86_attr" "perm2")
+ (eq_attr "mode" "V4SF,V2DF,TI"))
+ (and (eq_attr "c86_attr" "perm")
+ (eq_attr "mode" "V8SF,V4DF,TI,OI")))
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+
+(define_insn_reservation "c86_4g_m7_avx512_perm_xmm_opload" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (ior (and (eq_attr "c86_attr" "perm2")
+ (eq_attr "mode" "V4SF,V2DF,TI"))
+ (and (eq_attr "c86_attr" "perm")
+ (eq_attr "mode" "V8SF,V4DF,TI,OI")))
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+
+(define_insn_reservation "c86_4g_m7_avx512_permi2_ymm" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm2")
+ (and (eq_attr "mode" "V8SF,V4DF,OI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_permi2_zmm" 16
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm2")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_permi2_ymm_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm2")
+ (and (eq_attr "mode" "V8SF,V4DF,OI")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_avx512_permi2_zmm_load" 23
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm2")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (match_operand 2 "immediate_operand")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4")
+
+(define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (match_operand 2 "immediate_operand")
+ (eq_attr "memory" "load"))))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
+
+(define_insn_reservation "c86_4g_m7_avx512_perm_zmm_noimm" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (match_operand 2 "nonimmediate_operand")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_sse_perm_zmm_noimm_load" 15
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (match_operand 2 "nonimmediate_operand")
+ (eq_attr "memory" "load"))))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_avx_perm_ymm" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx_perm_ymem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "perm")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+;; VINSERT
+(define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,sselog1")
+ (and (eq_attr "c86_attr" "insertx")
+ (and (eq_attr "mode" "V8SF,V4DF,OI")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
+
+(define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,sselog1")
+ (and (eq_attr "c86_attr" "insertx")
+ (and (eq_attr "mode" "V8SF,V4DF,OI")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "load,both"))))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
+
+(define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "insertx")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
+ (match_operand 2 "register_operand"))))))
+ "c86-4g-m7-double,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4")
+
+(define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "insertx")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
+ (match_operand 2 "memory_operand"))))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4")
+
+(define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "insertx")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
+ (match_operand 2 "register_operand"))))))
+ "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_insertx_zymem" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "insertx")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
+ (match_operand 2 "memory_operand"))))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx_insertx_ymm" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,sselog1")
+ (and (eq_attr "c86_attr" "insertx")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu0*2")
+
+(define_insn_reservation "c86_4g_m7_avx_insertx_ymem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,sselog1")
+ (and (eq_attr "c86_attr" "insertx")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0*2")
+
+;; SHUF/MULTISHIFTQB
+(define_insn_reservation "c86_4g_m7_avx512_shuf_xymm" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "shufx")
+ (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+
+(define_insn_reservation "c86_4g_m7_avx512_shuf_zmm" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "shufx")
+ (and (eq_attr "mode" "V8DF,V16SF,XI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_shuf_xymem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "shufx")
+ (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+
+(define_insn_reservation "c86_4g_m7_avx512_shuf_zmem" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "shufx")
+ (and (eq_attr "mode" "V8DF,V16SF,XI")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+;; SSELOGIC
+(define_insn_reservation "c86_4g_m7_sselogic_xymm" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,sselog1")
+ (and (eq_attr "c86_attr" "sselogic")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_sselogic_xymm_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,sselog1")
+ (and (eq_attr "c86_attr" "sselogic")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+
+;; CMPESTR
+(define_insn_reservation "c86_4g_m7_avx512_cmpestr" 6
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "cmpestr")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_cmpestr_load" 13
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "cmpestr")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+;; SSELOG
+(define_insn_reservation "c86_4g_m7_avx512_log" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_log_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+
+;; SSELOG1
+;; VDBPSADBW
+(define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymm" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "sadbw")
+ (and (eq_attr "mode" "OI,TI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymem" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "sadbw")
+ (and (eq_attr "mode" "OI,TI")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmm" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "sadbw")
+ (and (eq_attr "mode" "XI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmem" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "sadbw")
+ (and (eq_attr "mode" "XI")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+;; ABS
+(define_insn_reservation "c86_4g_m7_avx512_abs" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1,sse")
+ (and (eq_attr "c86_attr" "abs")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_avx512_abs_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1,sse")
+ (and (eq_attr "c86_attr" "abs")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "load,both")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+
+;; SIGN
+(define_insn_reservation "c86_4g_m7_avx_sign" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "sign")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_avx_sign_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "sign")
+ (eq_attr "memory" "!none"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+
+;; BLEND/ABS/AES
+(define_insn_reservation "c86_4g_m7_avx_blend" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "abs,blend,aes")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_avx_blend_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "abs,blend,aes")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_avx512_aes" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1,ssecvt,sse")
+ (and (eq_attr "c86_attr" "aes")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_aes_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1,ssecvt,sse")
+ (and (eq_attr "c86_attr" "aes")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx_aes" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "aes")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_avx_aes_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "aes")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+
+;; EXTR
+(define_insn_reservation "c86_4g_m7_extr" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1,sselog,mmxcvt")
+ (and (eq_attr "c86_attr" "extr")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_extr_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sselog1,sselog,mmxcvt")
+ (and (eq_attr "c86_attr" "extr")
+ (eq_attr "memory" "!none"))))
+ "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+
+;; SSECOMI
+(define_insn_reservation "c86_4g_m7_avx_ssecomi_comi" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecomi")
+ (and (eq_attr "prefix_extra" "0")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-double,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_avx_ssecomi_comi_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecomi")
+ (and (eq_attr "prefix_extra" "0")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_avx_ssecomi_test" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecomi")
+ (and (eq_attr "prefix_extra" "1")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+
+(define_insn_reservation "c86_4g_m7_avx_ssecomi_test_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecomi")
+ (and (eq_attr "prefix_extra" "1")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+
+;; SSEIMUL
+(define_insn_reservation "c86_4g_m7_avx512_imul" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseimul")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx512_imul_mem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseimul")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx_imul" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseimul")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_avx_imul_mem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseimul")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+
+;; SSEMOV
+(define_insn_reservation "c86_4g_m7_avx512_mov_vmov" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov,sseiadd")
+ (and (eq_attr "c86_attr" "other,blend,maxmin")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_avx512_mov_vmov_store" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "store"))))
+ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_avx512_mov_vmov_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov,sseiadd")
+ (and (eq_attr "c86_attr" "other,blend,maxmin")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_avx512_vpmovx_y" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "vpmovx")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "mode" "OI,V8SF,V4DF")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+
+(define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov,sselog1")
+ (and (eq_attr "c86_attr" "vpmovx")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "mode" "OI,V8SF,V4DF")
+ (eq_attr "memory" "load,both"))))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+
+(define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "vpmovx")
+ (and (eq_attr "mode" "XI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4")
+
+(define_insn_reservation "c86_4g_m7_avx512_vpmovx_z_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "vpmovx")
+ (and (eq_attr "mode" "XI")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
+
+(define_insn_reservation "c86_4g_m7_avx512_vpmovx_x" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "vpmovx")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "mode" "TI,SI")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_vpmovx_x_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "vpmovx")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "mode" "TI,SI")
+ (eq_attr "memory" "load"))))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx_vpmovx_xx" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "vpmovx")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+
+(define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "vpmovx")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "load,both")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+
+;; EXPAND
+(define_insn_reservation "c86_4g_m7_avx512_expand" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "expand,compress")
+ (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu3*2,c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2")
+
+(define_insn_reservation "c86_4g_m7_avx512_expand_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "expand,compress")
+ (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3*2,c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2")
+
+(define_insn_reservation "c86_4g_m7_avx512_expand_z" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "expand,compress")
+ (and (eq_attr "mode" "XI,V16SF,V8DF")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_expand_z_load" 17
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "expand,compress")
+ (and (eq_attr "mode" "XI,V16SF,V8DF")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+;; MOVNT
+(define_insn_reservation "c86_4g_m7_avx512_movnt_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "movnt")
+ (and (eq_attr "mode" "XI,V16SF,V8DF")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-double,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_avx512_movnt_store" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "movnt")
+ (and (eq_attr "mode" "XI,V16SF,V8DF")
+ (eq_attr "memory" "store")))))
+ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1*2")
+
+(define_insn_reservation "c86_4g_m7_sse_movnt_store" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov,mmxmov")
+ (and (eq_attr "c86_attr" "movnt")
+ (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ (eq_attr "memory" "!none")))))
+ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_sse_movnt_xy" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "movnt")
+ (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+
+;; BLENDV
+(define_insn_reservation "c86_4g_m7_avx512_blendv" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "blendv")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_avx512_blendv_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov")
+ (and (eq_attr "c86_attr" "blendv")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+
+;; SSEMOV2
+(define_insn_reservation "c86_4g_m7_sse_mov2" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov2")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-direct,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_sse_mov2_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemov2")
+ (eq_attr "memory" "!none")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+
+;; SSEISHFT
+(define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseishft")
+ (and (eq_attr "prefix_extra" "1")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseishft")
+ (and (eq_attr "prefix_extra" "1")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseishft")
+ (and (eq_attr "prefix_extra" "!1")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseishft")
+ (and (eq_attr "prefix_extra" "!1")
+ (eq_attr "memory" "!none"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+
+
+;; SSEADD
+(define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd,sse")
+ (and (eq_attr "c86_attr" "maxmin")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "memory" "none")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd,sse")
+ (and (eq_attr "c86_attr" "maxmin")
+ (and (eq_attr "prefix" "evex")
+ (ior (eq_attr "memory" "load")
+ (eq_attr "memory" "load"))))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd,sse")
+ (and (eq_attr "c86_attr" "maxmin")
+ (and (eq_attr "prefix" "vex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd,sse")
+ (and (eq_attr "c86_attr" "maxmin")
+ (and (eq_attr "prefix" "vex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd,sse")
+ (and (eq_attr "c86_attr" "maxmin")
+ (and (eq_attr "prefix" "orig")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd,sse")
+ (and (eq_attr "c86_attr" "maxmin")
+ (and (eq_attr "prefix" "orig")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+
+;; SUB/ADD
+(define_insn_reservation "c86_4g_m7_avx512_sseadd_xy" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_avx512_sseadd_xy_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3")
+
+;; HADD/HSUB
+(define_insn_reservation "c86_4g_m7_avx_sseadd_hplus" 7
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd,sseadd1")
+ (and (eq_attr "c86_attr" "hplus")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx_sseadd_hplus_load" 14
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseadd,sseadd1")
+ (and (eq_attr "c86_attr" "hplus")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+;; SSEIADD
+(define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "sadbw,madd")
+ (and (ior (eq_attr "prefix" "evex")
+ (eq_attr "mode" "XI"))
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd_mem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "sadbw,madd")
+ (and (ior (eq_attr "prefix" "evex")
+ (eq_attr "mode" "XI"))
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "sadbw")
+ (and (eq_attr "prefix" "vex,maybe_evex")
+ (and (eq_attr "mode" "TI,OI")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw_mem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "sadbw")
+ (and (eq_attr "prefix" "vex,maybe_evex")
+ (and (eq_attr "mode" "TI,OI")
+ (eq_attr "memory" "load"))))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "sadbw")
+ (and (eq_attr "prefix" "orig")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "sadbw")
+ (and (eq_attr "prefix" "orig")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "madd")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu0")
+
+(define_insn_reservation "c86_4g_m7_sse_sseiadd_madd_mem" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "madd")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+
+;; AVG
+(define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "avg")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "avg")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd,sseiadd1")
+ (and (eq_attr "c86_attr" "hplus")
+ (and (eq_attr "prefix" "vex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd,sseiadd1")
+ (and (eq_attr "c86_attr" "hplus")
+ (and (eq_attr "prefix" "vex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd,sseiadd1")
+ (and (eq_attr "c86_attr" "hplus")
+ (and (eq_attr "prefix" "orig")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector,c86-4g-m7-fpu0*2")
+
+(define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sseiadd,sseiadd1")
+ (and (eq_attr "c86_attr" "hplus")
+ (and (eq_attr "prefix" "orig")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu0*2")
+
+;; SSEMUL
+(define_insn_reservation "c86_4g_m7_avx512_ssemul" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemul")
+ (eq_attr "memory" "none")))
+ "c86-4g-m7-direct,c86-4g-m7-fpu0")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssemul_load" 10
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemul")
+ (eq_attr "memory" "load")))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+
+;; SSEDIV
+(define_insn_reservation "c86_4g_m7_avx512_ssediv" 13
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssediv")
+ (and (not (eq_attr "mode" "V16SF,V8DF"))
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu3*7")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssediv_mem" 20
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssediv")
+ (and (not (eq_attr "mode" "V16SF,V8DF"))
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3*7")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssediv_z" 24
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssediv")
+ (and (eq_attr "mode" "V16SF,V8DF")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-double,c86-4g-m7-fpu3*7")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssediv")
+ (and (eq_attr "mode" "V16SF,V8DF")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu3*7")
+
+;; SSECMP
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp_z" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp_z_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "mode" "V16SF,V8DF,XI")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "mode" "TI,OI")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "mode" "TI,OI")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "load"))))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx_ssecmp_vp" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu")
+
+(define_insn_reservation "c86_4g_m7_avx_ssecmp_vp_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+
+;; VPTEST
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp_test" 6
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "mode" "TI,OI")
+ (and (eq_attr "c86_attr" "ptest")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "mode" "TI,OI")
+ (and (eq_attr "c86_attr" "ptest")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_z" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "mode" "XI")
+ (and (eq_attr "c86_attr" "ptest")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_z_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecmp")
+ (and (eq_attr "mode" "XI")
+ (and (eq_attr "c86_attr" "ptest")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+;; SSECVT
+(define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
+ (and (not (ior (match_operand:V8DI 1 "register_operand")
+ (match_operand:V8DF 1 "register_operand")))
+ (eq_attr "memory" "none")))))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
+ (and (not (ior (match_operand:V8DI 1 "register_operand")
+ (match_operand:V8DF 1 "register_operand")))
+ (eq_attr "memory" "!none")))))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "mode" "OI,V8SF,V4DF")
+ (and (eq_attr "c86_attr" "other")
+ (and (ior (match_operand:V8DI 1 "register_operand")
+ (match_operand:V8DF 1 "register_operand"))
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z_load" 15
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "mode" "OI,V8SF,V4DF")
+ (and (eq_attr "c86_attr" "other")
+ (and (ior (match_operand:V8DI 1 "memory_operand")
+ (match_operand:V8DF 1 "memory_operand"))
+ (eq_attr "memory" "!none"))))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecvt_z" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "mode" "XI,V16SF,V8DF")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_ssecvt_z_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "mode" "XI,V16SF,V8DF")
+ (eq_attr "memory" "!none")))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx_ssecvt" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "prefix" "!evex")
+ (and (eq_attr "mmx_isa" "base")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+
+(define_insn_reservation "c86_4g_m7_avx_ssecvt_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "prefix" "!evex")
+ (and (eq_attr "mmx_isa" "base")
+ (eq_attr "memory" "!none")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+
+;; CVTPI
+(define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "mode" "SF,DI")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "mode" "SF,DI")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+
+(define_insn_reservation "c86_4g_m7_sse_ssecvt_pi" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (not (eq_attr "mode" "SF,DI"))
+ (and (eq_attr "mmx_isa" "native")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_sse_ssecvt_pi_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssecvt")
+ (and (not (eq_attr "mode" "SF,DI"))
+ (and (eq_attr "mmx_isa" "native")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+
+;; SSEMULADD
+(define_insn_reservation "c86_4g_m7_avx512_muladd" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemuladd")
+ (and (eq_attr "c86_attr" "other")
+ (and (not (eq_attr "isa" "fma,fma4"))
+ (eq_attr "mode" "V32HF,V16SF,V8DF,XI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx512_muladd_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemuladd")
+ (and (eq_attr "c86_attr" "other")
+ (and (not (eq_attr "isa" "fma,fma4"))
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx512_muladd_madd" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemuladd,sse")
+ (and (eq_attr "c86_attr" "madd,rcp")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx512_muladd_madd_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemuladd,sse")
+ (and (eq_attr "c86_attr" "madd,rcp")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_fma_muladd" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemuladd")
+ (and (eq_attr "isa" "fma,fma4")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_fma_muladd_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "ssemuladd")
+ (and (eq_attr "isa" "fma,fma4")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+
+;; SSE
+(define_insn_reservation "c86_4g_m7_avx512_sse_range" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "length_immediate" "!1")
+ (and (eq_attr "prefix" "evex")
+ (and (eq_attr "c86_decode" "direct")
+ (eq_attr "memory" "none")))))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_range_load" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "length_immediate" "!1")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "prefix" "evex")
+ (eq_attr "memory" "load")))))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x" 2
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_decode" "vector")
+ (and (eq_attr "mode" "TI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x_load" 9
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_decode" "vector")
+ (and (eq_attr "mode" "TI")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_decode" "vector")
+ (and (eq_attr "mode" "OI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_decode" "vector")
+ (and (eq_attr "mode" "OI")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_decode" "vector")
+ (and (eq_attr "mode" "XI")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z_load" 15
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_decode" "vector")
+ (and (eq_attr "mode" "XI")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_class" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "length_immediate" "1")
+ (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_class_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "length_immediate" "1")
+ (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
+ (eq_attr "memory" "load"))))))
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_class_z" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "length_immediate" "1")
+ (and (eq_attr "mode" "V32HF,V16SF,V8DF")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_class_z_load" 11
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "other")
+ (and (eq_attr "length_immediate" "1")
+ (and (eq_attr "mode" "V32HF,V16SF,V8DF")
+ (eq_attr "memory" "load"))))))
+ "c86-4g-m7-vector,c86-4g-m7-load")
+
+(define_insn_reservation "c86_4g_m7_avx_sse" 5
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "rcp,other")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "none")))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_avx_sse_load" 12
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "rcp,other")
+ (and (eq_attr "prefix" "!evex")
+ (eq_attr "memory" "load")))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt" 16
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "sqrt")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7")
+
+(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_load" 23
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "c86_attr" "sqrt")
+ (eq_attr "memory" "load"))))
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7")
+
+;; MSKLOG/MSKMOV
+(define_insn_reservation "c86_4g_m7_avx512_msklog" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "msklog")
+ (eq_attr "c86_decode" "direct")))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_msklog_vector" 4
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "msklog")
+ (eq_attr "c86_decode" "vector")))
+ "c86-4g-m7-vector")
+
+(define_insn_reservation "c86_4g_m7_avx512_mskmov_reg_k" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mskmov")
+ (and (match_operand 0 "register_operand" "r")
+ (eq_attr "memory" "none"))))
+ "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_mskmov_xy_k" 2
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mskmov")
+ (ior (match_operand:V2DI 0 "register_operand" "v")
+ (match_operand:V4DI 0 "register_operand" "v"))))
+ "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_mskmov_z_k" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mskmov")
+ (match_operand:V8DI 0 "register_operand" "v")))
+ "c86-4g-m7-vector,c86-4g-m7-fpu3*2,c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2")
+
+(define_insn_reservation "c86_4g_m7_avx512_mskmov_k_k" 1
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mskmov")
+ (and (match_operand 0 "register_operand" "k")
+ (match_operand 1 "register_operand" "k"))))
+ "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+
+(define_insn_reservation "c86_4g_m7_avx512_mskmov_k_reg" 3
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mskmov")
+ (and (match_operand 0 "register_operand" "k")
+ (match_operand 1 "register_operand" "r"))))
+ "c86-4g-m7-double,c86-4g-m7-fpu1*2,c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2")
+
+(define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 8
+ (and (eq_attr "cpu" "c86_4g_m7")
+ (and (eq_attr "type" "mskmov")
+ (and (match_operand 0 "register_operand" "k")
+ (match_operand 1 "memory_operand"))))
+ "c86-4g-m7-direct,c86-4g-m7-load")
--- /dev/null
+;; Copyright (C) 2026 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+;;
+
+
+(define_attr "c86_decode" "direct,vector,double"
+ (const_string "direct"))
+
+(define_attr "c86_attr" "other,abs,sqrt,maxmin,blend,blendv,rcp,movnt,avg,
+ sign,sadbw,insr,perm2,perm,insertx,shufx,madd,
+ compress,sselogic,cmpestr,extr,vpmovx,expand,aes,
+ hplus,ptest"
+ (const_string "other"))
+
+;; HYGON Scheduling
+;; Modeling automatons for decoders, integer execution pipes,
+;; AGU pipes and floating point execution units.
+(define_automaton "c86_4g, c86_4g_ieu, c86_4g_fp, c86_4g_agu")
+
+;; Decoders unit has 4 decoders and all of them can decode fast path
+;; and vector type instructions.
+(define_cpu_unit "c86-4g-decode0" "c86_4g")
+(define_cpu_unit "c86-4g-decode1" "c86_4g")
+(define_cpu_unit "c86-4g-decode2" "c86_4g")
+(define_cpu_unit "c86-4g-decode3" "c86_4g")
+
+;; Currently blocking all decoders for vector path instructions as
+;; they are dispatched separetely as microcode sequence.
+;; Fix me: Need to revisit this.
+(define_reservation "c86-4g-vector" "c86-4g-decode0+c86-4g-decode1+c86-4g-decode2+c86-4g-decode3")
+
+;; Direct instructions can be issued to any of the four decoders.
+(define_reservation "c86-4g-direct" "c86-4g-decode0|c86-4g-decode1|c86-4g-decode2|c86-4g-decode3")
+
+;; Fix me: Need to revisit this later to simulate fast path double behavior.
+(define_reservation "c86-4g-double" "c86-4g-direct")
+
+
+;; Integer unit 4 ALU pipes.
+(define_cpu_unit "c86-4g-ieu0" "c86_4g_ieu")
+(define_cpu_unit "c86-4g-ieu1" "c86_4g_ieu")
+(define_cpu_unit "c86-4g-ieu2" "c86_4g_ieu")
+(define_cpu_unit "c86-4g-ieu3" "c86_4g_ieu")
+(define_reservation "c86-4g-ieu" "c86-4g-ieu0|c86-4g-ieu1|c86-4g-ieu2|c86-4g-ieu3")
+
+;; 2 AGU pipes in c86_4g
+;; According to CPU diagram last AGU unit is used only for stores.
+(define_cpu_unit "c86-4g-agu0" "c86_4g_agu")
+(define_cpu_unit "c86-4g-agu1" "c86_4g_agu")
+(define_reservation "c86-4g-agu-reserve" "c86-4g-agu0|c86-4g-agu1")
+
+;; Load is 4 cycles. We do not model reservation of load unit.
+;;(define_reservation "c86-4g-load" "c86-4g-agu-reserve, nothing, nothing, nothing")
+(define_reservation "c86-4g-load" "c86-4g-agu-reserve")
+(define_reservation "c86-4g-store" "c86-4g-agu-reserve")
+
+;; vectorpath (microcoded) instructions are single issue instructions.
+;; So, they occupy all the integer units.
+(define_reservation "c86-4g-ivector" "c86-4g-ieu0+c86-4g-ieu1
+ +c86-4g-ieu2+c86-4g-ieu3
+ +c86-4g-agu0+c86-4g-agu1")
+
+;; Floating point unit 4 FP pipes.
+(define_cpu_unit "c86-4g-fp0" "c86_4g_fp")
+(define_cpu_unit "c86-4g-fp1" "c86_4g_fp")
+(define_cpu_unit "c86-4g-fp2" "c86_4g_fp")
+(define_cpu_unit "c86-4g-fp3" "c86_4g_fp")
+
+(define_reservation "c86-4g-fpu" "c86-4g-fp0|c86-4g-fp1|c86-4g-fp2|c86-4g-fp3")
+
+(define_reservation "c86-4g-fvector" "c86-4g-fp0+c86-4g-fp1
+ +c86-4g-fp2+c86-4g-fp3
+ +c86-4g-agu0+c86-4g-agu1")
+
+;; Call instruction
+(define_insn_reservation "c86_4g_call" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "type" "call,callv"))
+ "c86-4g-double,c86-4g-store,c86-4g-ieu0+c86-4g-ieu3")
+
+;; General instructions
+(define_insn_reservation "c86_4g_push" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "push")
+ (eq_attr "memory" "store")))
+ "c86-4g-direct,c86-4g-store")
+
+(define_insn_reservation "c86_4g_push_load" 4
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "push")
+ (eq_attr "memory" "both")))
+ "c86-4g-direct,c86-4g-load+c86-4g-store")
+
+(define_insn_reservation "c86_4g_pop" 4
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "pop")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load")
+
+(define_insn_reservation "c86_4g_pop_mem" 4
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "pop")
+ (eq_attr "memory" "both")))
+ "c86-4g-direct,c86-4g-load,c86-4g-store")
+
+;; Leave
+(define_insn_reservation "c86_4g_leave" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "type" "leave"))
+ "c86-4g-double,c86-4g-ieu+c86-4g-store")
+
+;; Integer Instructions or General instructions
+;; Multiplications
+;; Reg operands
+(define_insn_reservation "c86_4g_imul" 3
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "imul")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-ieu1")
+
+(define_insn_reservation "c86_4g_imul_mem" 7
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "imul")
+ (eq_attr "memory" "!none")))
+ "c86-4g-direct,c86-4g-load, c86-4g-ieu1")
+
+;; Divisions
+;; Reg operands
+(define_insn_reservation "c86_4g_idiv_DI" 41
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "DI")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-ieu2*41")
+
+(define_insn_reservation "c86_4g_idiv_SI" 25
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "SI")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-ieu2*25")
+
+(define_insn_reservation "c86_4g_idiv_HI" 17
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "HI")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-ieu2*17")
+
+(define_insn_reservation "c86_4g_idiv_QI" 15
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "QI")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-ieu2*15")
+
+;; Mem operands
+(define_insn_reservation "c86_4g_idiv_mem_DI" 45
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "DI")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-ieu2*41")
+
+(define_insn_reservation "c86_4g_idiv_mem_SI" 29
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "SI")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-ieu2*25")
+
+(define_insn_reservation "c86_4g_idiv_mem_HI" 21
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "HI")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-ieu2*17")
+
+(define_insn_reservation "c86_4g_idiv_mem_QI" 19
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "idiv")
+ (and (eq_attr "mode" "QI")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-ieu2*15")
+
+;; STR ISHIFT which are micro coded.
+;; Fix me: Latency need to be rechecked.
+(define_insn_reservation "c86_4g_str_ishift" 6
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "str,ishift")
+ (eq_attr "memory" "both,store")))
+ "c86-4g-vector,c86-4g-ivector")
+
+;; MOV - integer moves
+(define_insn_reservation "c86_4g_load_imov_double" 2
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "double")
+ (and (eq_attr "type" "imovx")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-ieu")
+
+(define_insn_reservation "c86_4g_load_imov_direct" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "!double")
+ (and (eq_attr "type" "imov,imovx")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-ieu")
+
+(define_insn_reservation "c86_4g_load_imov_double_store" 2
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "double")
+ (and (eq_attr "type" "imovx")
+ (eq_attr "memory" "store"))))
+ "c86-4g-double,c86-4g-ieu,c86-4g-store")
+
+(define_insn_reservation "c86_4g_load_imov_direct_store" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "!double")
+ (and (eq_attr "type" "imov,imovx")
+ (eq_attr "memory" "store"))))
+ "c86-4g-direct,c86-4g-ieu,c86-4g-store")
+
+(define_insn_reservation "c86_4g_load_imov_double_load" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "double")
+ (and (eq_attr "type" "imovx")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-ieu")
+
+(define_insn_reservation "c86_4g_load_imov_direct_load" 4
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "!double")
+ (and (eq_attr "type" "imov,imovx")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load")
+
+;; INTEGER/GENERAL instructions
+;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST
+(define_insn_reservation "c86_4g_insn" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
+ (eq_attr "memory" "none,unknown")))
+ "c86-4g-direct,c86-4g-ieu")
+
+(define_insn_reservation "c86_4g_insn_load" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-ieu")
+
+;; FIXME: The instructions matched here has only two operands, which means memory type can only be none, load or both.
+;; Store memory type handling should never take effect here?
+(define_insn_reservation "c86_4g_insn_store" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
+ (eq_attr "memory" "store")))
+ "c86-4g-direct,c86-4g-ieu,c86-4g-store")
+
+(define_insn_reservation "c86_4g_insn_both" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
+ (eq_attr "memory" "both")))
+ "c86-4g-direct,c86-4g-load,c86-4g-ieu,c86-4g-store")
+
+;; Special latency for multi type.
+(define_insn_reservation "c86_4g_fp_fcomp" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "unit" "i387")
+ (eq_attr "type" "multi"))))
+ "c86-4g-double,c86-4g-fp0|c86-4g-fp2")
+
+;; Fix me: Other vector type insns keeping latency 6 as of now.
+(define_insn_reservation "c86_4g_ieu_vector" 6
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "unit" "!i387")
+ (eq_attr "type" "other,str,multi"))))
+ "c86-4g-vector,c86-4g-ivector")
+
+;; ALU1 register operands.
+(define_insn_reservation "c86_4g_alu1_vector" 3
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "vector")
+ (and (eq_attr "type" "alu1")
+ (eq_attr "memory" "none,unknown"))))
+ "c86-4g-vector,c86-4g-ivector")
+
+(define_insn_reservation "c86_4g_alu1_double" 2
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "double")
+ (and (eq_attr "type" "alu1")
+ (eq_attr "memory" "none,unknown"))))
+ "c86-4g-double,c86-4g-ieu")
+
+(define_insn_reservation "c86_4g_alu1_direct" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "type" "alu1")
+ (eq_attr "memory" "none,unknown"))))
+ "c86-4g-direct,c86-4g-ieu")
+
+;; Branches : Fix me need to model conditional branches.
+(define_insn_reservation "c86_4g_branch" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "ibr")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct")
+
+;; Indirect branches check latencies.
+(define_insn_reservation "c86_4g_indirect_branch_mem" 6
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "ibr")
+ (eq_attr "memory" "load")))
+ "c86-4g-vector,c86-4g-ivector")
+
+;; LEA executes in ALU units with 1 cycle latency.
+(define_insn_reservation "c86_4g_lea" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "type" "lea"))
+ "c86-4g-direct,c86-4g-ieu")
+
+;; Floating point
+(define_insn_reservation "c86_4g_fp_cmov" 6
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "type" "fcmov"))
+ "c86-4g-vector,c86-4g-fvector")
+
+
+(define_insn_reservation "c86_4g_fp_mov_direct_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_fp_mov_direct_store" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "store"))))
+ "c86-4g-direct,c86-4g-fp2|c86-4g-fp3,c86-4g-store")
+
+(define_insn_reservation "c86_4g_fp_mov_double" 4
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "double")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_fp_mov_double_load" 12
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "double")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_fp_mov_direct" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "type" "fmov")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fp1")
+
+;; SQRT
+(define_insn_reservation "c86_4g_fp_sqrt" 22
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "fpspc")
+ (eq_attr "c86_attr" "sqrt")))
+ "c86-4g-direct,c86-4g-fp1*22")
+
+(define_insn_reservation "c86_4g_sse_sqrt_sf" 14
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "SF,V4SF,V8SF")
+ (and (eq_attr "memory" "none,unknown")
+ (and (eq_attr "c86_attr" "sqrt")
+ (eq_attr "type" "sse")))))
+ "c86-4g-direct,c86-4g-fp1*14")
+
+(define_insn_reservation "c86_4g_sse_sqrt_sf_mem" 21
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "SF,V4SF,V8SF")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "c86_attr" "sqrt")
+ (eq_attr "type" "sse")))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1*14")
+
+(define_insn_reservation "c86_4g_sse_sqrt_df" 20
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "DF,V2DF,V4DF")
+ (and (eq_attr "memory" "none,unknown")
+ (and (eq_attr "c86_attr" "sqrt")
+ (eq_attr "type" "sse")))))
+ "c86-4g-direct,c86-4g-fp1*20")
+
+(define_insn_reservation "c86_4g_sse_sqrt_df_mem" 27
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "DF,V2DF,V4DF")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "c86_attr" "sqrt")
+ (eq_attr "type" "sse")))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1*20")
+
+;; RCP
+(define_insn_reservation "c86_4g_sse_rcp" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V4SF,V8SF,SF")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "c86_attr" "rcp")
+ (eq_attr "type" "sse")))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_sse_rcp_mem" 12
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V4SF,V8SF,SF")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "c86_attr" "rcp")
+ (eq_attr "type" "sse")))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+
+;; TODO: AGU?
+(define_insn_reservation "c86_4g_fp_spc_direct" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_decode" "direct")
+ (and (eq_attr "type" "fpspc")
+ (eq_attr "memory" "store"))))
+ "c86-4g-direct,c86-4g-fp3")
+
+;; FABS
+(define_insn_reservation "c86_4g_fp_absneg" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "type" "fsgn"))
+ "c86-4g-direct,c86-4g-fp1|c86-4g-fp3")
+
+;; FCMP
+(define_insn_reservation "c86_4g_fp_fcmp" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "memory" "none")
+ (and (eq_attr "c86_decode" "double")
+ (eq_attr "type" "fcmp"))))
+ "c86-4g-double,c86-4g-fp0,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_fp_fcmp_load" 12
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "memory" "load")
+ (and (eq_attr "c86_decode" "double")
+ (eq_attr "type" "fcmp"))))
+ "c86-4g-double,c86-4g-load, c86-4g-fp0,c86-4g-fp1")
+
+;;FADD FSUB FMUL
+(define_insn_reservation "c86_4g_fp_op_mul" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "fop,fmul")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_fp_op_mul_load" 12
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "fop,fmul")
+ (and (eq_attr "fp_int_src" "false")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_fp_op_imul_load" 16
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "fop,fmul")
+ (and (eq_attr "fp_int_src" "true")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp0,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_fp_op_div" 15
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp1*15")
+
+(define_insn_reservation "c86_4g_fp_op_div_load" 22
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1*15")
+
+(define_insn_reservation "c86_4g_fp_op_idiv_load" 27
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "fdiv")
+ (and (eq_attr "fp_int_src" "true")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp1*19")
+
+;; MMX, SSE, SSEn.n, AVX, AVX2 instructions
+(define_insn_reservation "c86_4g_fp_insn" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "type" "mmx"))
+ "c86-4g-direct,c86-4g-fpu")
+
+(define_insn_reservation "c86_4g_mmx_add" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxadd")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1|c86-4g-fp3")
+
+(define_insn_reservation "c86_4g_mmx_add_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxadd")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1|c86-4g-fp3")
+
+(define_insn_reservation "c86_4g_mmx_hadd" 3
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseadd1")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_mmx_hadd_load" 10
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseadd1")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_mmx_cmp" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxcmp")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp3")
+
+(define_insn_reservation "c86_4g_mmx_cmp_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxcmp")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp3")
+
+(define_insn_reservation "c86_4g_mmx_cvt_pck_shuf" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_mmx_cvt_pck_shuf_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_mmx_shift" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxshft")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_mmx_move" 4
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxmov")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_mmx_shift_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxshft")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_mmx_move_load" 11
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxshft")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_mmx_move_store" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxshft,mmxmov")
+ (eq_attr "memory" "store,both")))
+ "c86-4g-direct,c86-4g-fp2,c86-4g-store")
+
+(define_insn_reservation "c86_4g_mmx_mul" 3
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxmul")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_mmx_mul_load" 10
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "mmxmul")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+
+;; sseabs
+(define_insn_reservation "c86_4g_sse_abs" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_attr" "abs")
+ (and (eq_attr "type" "sselog1")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-fpu")
+
+(define_insn_reservation "c86_4g_sse_pinsr_reg" 3
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "insr")
+ (and (match_operand 2 "register_operand")
+ (eq_attr "memory" "none")))))
+ "c86-4g-direct,c86-4g-ieu2,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_pinsr" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "insr")
+ (and (not (match_operand 2 "register_operand"))
+ (eq_attr "memory" "none")))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_log" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_log_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sselog")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_sign" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "sign")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fpu")
+
+(define_insn_reservation "c86_4g_sse_sign_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "sign")
+ (eq_attr "memory" "!none"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+
+
+(define_insn_reservation "c86_4g_sse_log1" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_log1_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sselog1")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "!none"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_extrq" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "memory" "none")
+ (eq_attr "prefix_data16" "1"))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_movsdup" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sse")
+ (and (eq_attr "memory" "none")
+ (eq_attr "prefix" "vex"))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_alignr" 1
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "prefix_extra" "1"))
+ (and (eq_attr "type" "sseishft")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_ishift" 1
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "prefix_extra" "!1"))
+ (and (eq_attr "type" "sseishft")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_ishift_load" 8
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "prefix_extra" "!1"))
+ (and (eq_attr "type" "sseishft")
+ (eq_attr "memory" "!none")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_insertimm" 3
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseins")
+ (and (eq_attr "memory" "none")
+ (eq_attr "length_immediate" "2"))))
+ "c86-4g-direct,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_sse_insert" 4
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseins")
+ (and (eq_attr "memory" "none")
+ (eq_attr "length_immediate" "!2"))))
+ "c86-4g-direct,c86-4g-fpu,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_sse_comi" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
+ (and (eq_attr "prefix" "!vex")
+ (and (eq_attr "prefix_extra" "0")
+ (and (eq_attr "type" "ssecomi")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp2,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_comi_load" 12
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ (and (eq_attr "prefix_extra" "0")
+ (and (eq_attr "type" "ssecomi")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_comi_double" 2
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V4SF,V2DF,TI"))
+ (and (eq_attr "prefix" "vex")
+ (and (eq_attr "prefix_extra" "0")
+ (and (eq_attr "type" "ssecomi")
+ (eq_attr "memory" "none")))))
+ "c86-4g-double,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_comi_double_load" 10
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V4SF,V2DF,TI"))
+ (and (eq_attr "prefix" "vex")
+ (and (eq_attr "prefix_extra" "0")
+ (and (eq_attr "type" "ssecomi")
+ (eq_attr "memory" "load")))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_test" 4
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ (and (eq_attr "prefix_extra" "1")
+ (and (eq_attr "type" "ssecomi")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_test_load" 11
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ (and (eq_attr "prefix_extra" "1")
+ (and (eq_attr "type" "ssecomi")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_avx256_test" 8
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V8SF,V4DF,OI"))
+ (and (eq_attr "prefix_extra" "1")
+ (and (eq_attr "type" "ssecomi")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_avx256_test_load" 15
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V8SF,V4DF,OI"))
+ (and (eq_attr "prefix_extra" "1")
+ (and (eq_attr "type" "ssecomi")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+
+;; SSE moves
+;; Fix me: Need to revist this again some of the moves may be restricted
+;; to some fpu pipes.
+
+;; movnt doesn't touch cache, so latency modeling has little impact.
+(define_insn_reservation "c86_4g_sse_movnt_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_attr" "movnt")
+ (and (eq_attr "type" "ssemov,mmxmov,ssecvt")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load")
+
+(define_insn_reservation "c86_4g_sse_movnt_store" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "c86_attr" "movnt")
+ (and (eq_attr "type" "ssemov,mmxmov,ssecvt")
+ (eq_attr "memory" "store"))))
+ "c86-4g-direct,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_sse_mov" 2
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "SI")
+ (and (eq_attr "isa" "avx")
+ (and (eq_attr "type" "ssemov")
+ (eq_attr "memory" "none")))))
+ "c86-4g-direct,c86-4g-ieu0")
+
+(define_insn_reservation "c86_4g_avx_mov" 2
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "TI")
+ (and (eq_attr "isa" "avx")
+ (and (eq_attr "type" "ssemov")
+ (and (match_operand:SI 1 "register_operand")
+ (eq_attr "memory" "none"))))))
+ "c86-4g-direct,c86-4g-ieu2")
+
+(define_insn_reservation "c86_4g_sseavx_mov" 1
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ (and (eq_attr "prefix_extra" "0")
+ (and (eq_attr "type" "ssemov")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fpu")
+
+(define_insn_reservation "c86_4g_sseavx_blend" 1
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ (and (eq_attr "type" "ssemov,sselog1")
+ (and (eq_attr "c86_attr" "blend,blendv")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_sseavx_mov_store" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
+ (and (eq_attr "type" "ssemov")
+ (eq_attr "memory" "store"))))
+ "c86-4g-direct,c86-4g-fpu,c86-4g-store")
+
+(define_insn_reservation "c86_4g_sseavx_mov_load" 8
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ (and (eq_attr "type" "ssemov")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+
+(define_insn_reservation "c86_4g_avx256_mov" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V8SF,V4DF,OI")
+ (and (eq_attr "type" "ssemov")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-fpu")
+
+(define_insn_reservation "c86_4g_avx256_mov_store" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V8SF,V4DF,OI")
+ (and (eq_attr "type" "ssemov")
+ (eq_attr "memory" "store"))))
+ "c86-4g-double,c86-4g-fpu,c86-4g-store")
+
+(define_insn_reservation "c86_4g_avx256_mov_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V8SF,V4DF,OI")
+ (and (eq_attr "type" "ssemov")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-fpu")
+
+;; SSE max & min
+(define_insn_reservation "c86_4g_sse_maxmin" 1
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V8SF,V2DF,V4DF,TI"))
+ (and (eq_attr "type" "sseadd")
+ (and (eq_attr "memory" "none")
+ (eq_attr "c86_attr" "maxmin"))))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_sse_maxmin_load" 8
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V8SF,V2DF,V4DF,TI"))
+ (and (eq_attr "type" "sseadd")
+ (and (eq_attr "memory" "load")
+ (eq_attr "c86_attr" "maxmin"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_sse_pmaxmin" 1
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "TI,OI"))
+ (and (eq_attr "type" "mmxadd,sseiadd")
+ (and (eq_attr "memory" "none")
+ (eq_attr "c86_attr" "maxmin"))))
+ "c86-4g-direct,c86-4g-fpu")
+
+(define_insn_reservation "c86_4g_sse_pmaxmin_load" 8
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "TI,OI"))
+ (and (eq_attr "type" "mmxadd,sseiadd")
+ (and (eq_attr "memory" "load")
+ (eq_attr "c86_attr" "maxmin"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+
+;; SSE avg
+(define_insn_reservation "c86_4g_sse_avg" 1
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "c86_attr" "avg"))
+ (and (eq_attr "type" "sseiadd,mmxshft")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fpu")
+
+(define_insn_reservation "c86_4g_sse_avg_load" 8
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "c86_attr" "avg"))
+ (and (eq_attr "type" "sseiadd,mmxshft")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp3")
+
+;;MMX sadbw
+(define_insn_reservation "c86_4g_sse_sadbw" 3
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseiadd,mmxshft")
+ (and (eq_attr "c86_attr" "sadbw")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_sse_sadbw_load" 10
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseiadd,mmxshft")
+ (and (eq_attr "c86_attr" "sadbw")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+
+;; SSE add
+(define_insn_reservation "c86_4g_sse_add" 3
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseadd")
+ (and (eq_attr "memory" "none")
+ (eq_attr "c86_attr" "other"))))
+ "c86-4g-direct,c86-4g-fp1|c86-4g-fp3")
+
+(define_insn_reservation "c86_4g_sse_add_load" 10
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseadd")
+ (and (eq_attr "memory" "load")
+ (eq_attr "c86_attr" "!maxmin"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1|c86-4g-fp3")
+
+(define_insn_reservation "c86_4g_sse_fma" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "ssemuladd")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_sse_fma_load" 12
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "ssemuladd")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_sse_iadd" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseiadd")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fpu")
+
+(define_insn_reservation "c86_4g_sse_iadd_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "sseiadd")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+
+;; SSE conversions.
+(define_insn_reservation "c86_4g_ssecvtsf_si_load" 12
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "SI")
+ (and (eq_attr "type" "sseicvt")
+ (and (match_operand:SF 1 "memory_operand")
+ (eq_attr "memory" "load")))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp3,c86-4g-ieu0")
+
+(define_insn_reservation "c86_4g_ssecvtdf_si" 5
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "SI")
+ (and (match_operand:DF 1 "register_operand")
+ (and (eq_attr "type" "sseicvt")
+ (eq_attr "memory" "none")))))
+ "c86-4g-double,c86-4g-fp3,c86-4g-ieu0")
+
+(define_insn_reservation "c86_4g_ssecvtdf_si_load" 12
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "SI")
+ (and (eq_attr "type" "sseicvt")
+ (and (match_operand:DF 1 "memory_operand")
+ (eq_attr "memory" "load")))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp3,c86-4g-ieu0")
+
+;; All other used ssecvt fp3 pipes
+;; Check: Need to revisit this again.
+;; Some SSE converts may use different pipe combinations.
+(define_insn_reservation "c86_4g_ssecvt" 4
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "none"))))
+ "c86-4g-direct,c86-4g-fp1")
+
+(define_insn_reservation "c86_4g_ssecvt_load" 11
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "type" "ssecvt")
+ (and (eq_attr "c86_attr" "other")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+
+;; SSE div
+(define_insn_reservation "c86_4g_ssediv_ss_ps" 10
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V4SF,SF"))
+ (and (eq_attr "type" "ssediv")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp1*10")
+
+(define_insn_reservation "c86_4g_ssediv_ss_ps_load" 17
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V4SF,SF"))
+ (and (eq_attr "type" "ssediv")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1*10")
+
+(define_insn_reservation "c86_4g_ssediv_sd_pd" 13
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V2DF,DF"))
+ (and (eq_attr "type" "ssediv")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp1*13")
+
+(define_insn_reservation "c86_4g_ssediv_sd_pd_load" 20
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V2DF,DF"))
+ (and (eq_attr "type" "ssediv")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1*13")
+
+
+(define_insn_reservation "c86_4g_ssediv_avx256_ps" 10
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V8SF")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "ssediv"))))
+ "c86-4g-double,c86-4g-fp1*10")
+
+(define_insn_reservation "c86_4g_ssediv_avx256_ps_load" 17
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V8SF")
+ (and (eq_attr "type" "ssediv")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp1*10")
+
+(define_insn_reservation "c86_4g_ssediv_avx256_pd" 13
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V4DF")
+ (and (eq_attr "type" "ssediv")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-fp1*13")
+
+(define_insn_reservation "c86_4g_ssediv_avx256_pd_load" 20
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V4DF")
+ (and (eq_attr "type" "ssediv")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp1*13")
+;; SSE MUL
+(define_insn_reservation "c86_4g_ssemul_ss_ps" 3
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V8SF,V4SF,SF"))
+ (and (eq_attr "type" "ssemul")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_ssemul_ss_ps_load" 10
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V8SF,V4SF,SF"))
+ (and (eq_attr "type" "ssemul")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_ssemul_sd_pd" 4
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V4DF,V2DF,DF"))
+ (and (eq_attr "type" "ssemul")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_ssemul_sd_pd_load" 11
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "V4DF,V2DF,DF"))
+ (and (eq_attr "type" "ssemul")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+
+;;SSE imul
+(define_insn_reservation "c86_4g_sseimul" 3
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "TI"))
+ (and (eq_attr "type" "sseimul")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_sseimul_avx256" 4
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "OI")
+ (and (eq_attr "type" "sseimul")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_sseimul_load" 10
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "TI"))
+ (and (eq_attr "type" "sseimul")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_sseimul_avx256_load" 11
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "OI")
+ (and (eq_attr "type" "sseimul")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_sseimul_di" 3
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "DI")
+ (and (eq_attr "memory" "none")
+ (eq_attr "type" "sseimul"))))
+ "c86-4g-direct,c86-4g-fp0")
+
+(define_insn_reservation "c86_4g_sseimul_load_di" 10
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "DI")
+ (and (eq_attr "type" "sseimul")
+ (eq_attr "memory" "load"))))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+
+;; SSE compares
+(define_insn_reservation "c86_4g_sse_cmp" 1
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ (and (eq_attr "type" "ssecmp")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_sse_cmp_load" 8
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ (and (eq_attr "type" "ssecmp")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+
+
+(define_insn_reservation "c86_4g_sse_cmp_avx256" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V8SF,V4DF")
+ (and (eq_attr "type" "ssecmp")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_sse_cmp_avx256_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "V8SF,V4DF")
+ (and (eq_attr "type" "ssecmp")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+
+(define_insn_reservation "c86_4g_sse_icmp" 1
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "QI,HI,SI,DI,TI"))
+ (and (eq_attr "type" "ssecmp")
+ (eq_attr "memory" "none")))
+ "c86-4g-direct,c86-4g-fpu")
+
+
+(define_insn_reservation "c86_4g_sse_icmp_load" 8
+ (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (eq_attr "mode" "QI,HI,SI,DI,TI"))
+ (and (eq_attr "type" "ssecmp")
+ (eq_attr "memory" "load")))
+ "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+
+
+(define_insn_reservation "c86_4g_sse_icmp_avx256" 1
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "OI")
+ (and (eq_attr "type" "ssecmp")
+ (eq_attr "memory" "none"))))
+ "c86-4g-double,c86-4g-fpu")
+
+
+(define_insn_reservation "c86_4g_sse_icmp_avx256_load" 8
+ (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ (and (eq_attr "mode" "OI")
+ (and (eq_attr "type" "ssecmp")
+ (eq_attr "memory" "load"))))
+ "c86-4g-double,c86-4g-load,c86-4g-fpu")
#define signature_SHANGHAI_ecx 0x20206961
#define signature_SHANGHAI_edx 0x68676e61
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_ecx 0x656e6975
+#define signature_HYGON_edx 0x6e65476e
+
#ifndef __x86_64__
/* At least one cpu (Winchip 2) does not set %ebx and %ecx
for cpuid leaf 1. Forcibly zero the two registers before
else
processor = PROCESSOR_PENTIUM;
}
+ else if (vendor == VENDOR_HYGON)
+ {
+ processor = PROCESSOR_GENERIC;
+ if (model == 4)
+ processor = PROCESSOR_C86_4G_M4;
+ else if (model == 6)
+ processor = PROCESSOR_C86_4G_M6;
+ else if (model >= 7)
+ processor = PROCESSOR_C86_4G_M7;
+ }
else if (vendor == VENDOR_CENTAUR)
{
processor = PROCESSOR_GENERIC;
case PROCESSOR_SHIJIDADAO:
cpu = "shijidadao";
break;
+ case PROCESSOR_C86_4G_M4:
+ cpu = "c86-4g-m4";
+ break;
+ case PROCESSOR_C86_4G_M6:
+ cpu = "c86-4g-m6";
+ break;
+ case PROCESSOR_C86_4G_M7:
+ cpu = "c86-4g-m7";
+ break;
default:
/* Use something reasonable. */
def_or_undef (parse_in, "__novalake");
def_or_undef (parse_in, "__novalake__");
break;
-
+ case PROCESSOR_C86_4G_M4:
+ def_or_undef (parse_in, "__c86_4g_m4");
+ def_or_undef (parse_in, "__c86_4g_m4__");
+ break;
+ case PROCESSOR_C86_4G_M6:
+ def_or_undef (parse_in, "__c86_4g_m6");
+ def_or_undef (parse_in, "__c86_4g_m6__");
+ break;
+ case PROCESSOR_C86_4G_M7:
+ def_or_undef (parse_in, "__c86_4g_m7");
+ def_or_undef (parse_in, "__c86_4g_m7__");
+ break;
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
break;
case PROCESSOR_NOVALAKE:
def_or_undef (parse_in, "__tune_novalake__");
break;
+ case PROCESSOR_C86_4G_M4:
+ def_or_undef (parse_in, "__tune_c86_4g_m4__");
+ break;
+ case PROCESSOR_C86_4G_M6:
+ def_or_undef (parse_in, "__tune_c86_4g_m6__");
+ break;
+ case PROCESSOR_C86_4G_M7:
+ def_or_undef (parse_in, "__tune_c86_4g_m7__");
+ break;
case PROCESSOR_INTEL:
case PROCESSOR_GENERIC:
break;
#define m_ZNVER (m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5 | m_ZNVER6)
#define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \
| m_ZNVER)
+#define m_C86_4G_M4 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M4)
+#define m_C86_4G_M6 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M6)
+#define m_C86_4G_M7 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M7)
+#define m_C86_4G (m_C86_4G_M4 | m_C86_4G_M6 | m_C86_4G_M7)
#define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC)
&znver3_cost, /* PROCESSOR_ZNVER3. */
&znver4_cost, /* PROCESSOR_ZNVER4. */
&znver5_cost, /* PROCESSOR_ZNVER5. */
- &znver5_cost /* PROCESSOR_ZNVER6. */
+ &znver5_cost, /* PROCESSOR_ZNVER6. */
+ &c86_4g_m4_cost, /* PROCESSOR_C86_4G_M4. */
+ &c86_4g_m6_cost, /* PROCESSOR_C86_4G_M6. */
+ &c86_4g_m7_cost /* PROCESSOR_C86_4G_M7. */
};
/* Guarantee that the array is aligned with enum processor_type. */
/* Znver1-4 Integer vector instructions execute in FP unit
and can execute 3 additions and one multiplication per cycle. */
if ((ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2
- || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4)
+ || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4
+ || ix86_tune == PROCESSOR_C86_4G_M4
+ || ix86_tune == PROCESSOR_C86_4G_M6
+ || ix86_tune == PROCESSOR_C86_4G_M7)
&& INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS)
return 1;
/* Znver5 can do 2 integer multiplications per cycle with latency
PROCESSOR_ZNVER4,
PROCESSOR_ZNVER5,
PROCESSOR_ZNVER6,
+ PROCESSOR_C86_4G_M4,
+ PROCESSOR_C86_4G_M6,
+ PROCESSOR_C86_4G_M7,
PROCESSOR_max
};
constexpr wide_int_bitmask PTA_YONGFENG = PTA_LUJIAZUI | PTA_AVX | PTA_AVX2
| PTA_F16C | PTA_FMA | PTA_SHA;
+constexpr wide_int_bitmask PTA_C86_4G_M4 = PTA_64BIT | PTA_MMX | PTA_SSE
+ | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3
+ | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+ | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
+ | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX
+ | PTA_RDSEED | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
+ | PTA_SHA | PTA_LZCNT | PTA_POPCNT;
+constexpr wide_int_bitmask PTA_C86_4G_M6 = PTA_C86_4G_M4;
+constexpr wide_int_bitmask PTA_C86_4G_M7 = PTA_C86_4G_M4 | PTA_AVX512F
+ | PTA_AVX512DQ | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL
+ | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI
+ | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ
+ | PTA_AVX512VP2INTERSECT | PTA_VAES | PTA_AVXVNNI | PTA_VPCLMULQDQ
+ | PTA_WBNOINVD | PTA_CLWB;
+
#ifndef GENERATOR_FILE
#include "insn-attr-common.h"
(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,
bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,
- znver5,znver6"
+ znver5,znver6,c86_4g_m4,c86_4g_m6,c86_4g_m7"
(const (symbol_ref "ix86_schedule")))
;; A basic instruction type. Refinements due to arguments to be
(include "haswell.md")
(include "lujiazui.md")
(include "yongfeng.md")
+(include "c86-4g.md")
+(include "c86-4g-m7.md")
\f
;; Operand and operator predicates and constraints
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "znver1_decode" "double")])
(define_insn "*cmpx<unord><MODEF:mode>"
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "double")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set (attr "enabled")
(if_then_else
(match_test ("SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"))
}
}
[(set_attr "type" "sselog1,sselog1,ssemov,ssemov")
+ (set_attr "c86_attr" "sselogic,sselogic,*,*")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
}
[(set_attr "isa" "*,avx2,*,*")
(set_attr "type" "sselog1,sselog1,ssemov,ssemov")
+ (set_attr "c86_attr" "sselogic,sselogic,*,*")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
(const_string "sselog1")
]
(const_string "ssemov")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "2,3")
+ (const_string "sselogic")
+ (const_string "*")))
(set (attr "prefix")
(if_then_else (eq_attr "type" "sselog1,ssemov")
(const_string "maybe_vex")
(const_string "lea")
]
(const_string "imov")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "12")
+ (const_string "sselogic")
+ (const_string "*")))
(set (attr "modrm")
(if_then_else
(and (eq_attr "alternative" "4") (eq_attr "type" "imov"))
(const_string "lea")
]
(const_string "imov")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "8")
+ (const_string "sselogic")
+ (const_string "*")))
(set (attr "prefix")
(if_then_else (eq_attr "type" "sselog1,ssemov")
(const_string "maybe_vex")
(const_string "imovx")
]
(const_string "imov")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "11")
+ (const_string "sselogic")
+ (const_string "*")))
(set (attr "prefix")
(cond [(eq_attr "alternative" "4,5,6,7,8")
(const_string "vex")
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "double")
+ (set_attr "c86_decode" "vector")
(set_attr "bdver1_decode" "double")])
(define_insn "*swap<mode>"
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "double")
+ (set_attr "c86_decode" "vector")
(set_attr "bdver1_decode" "double")])
(define_peephole2
}
[(set_attr "isa" "*,*,*,x64,x64")
(set_attr "type" "sselog1,ssemov,ssemov,multi,multi")
+ (set_attr "c86_attr" "sselogic,*,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "type" "sselog1,ssemov")
(const_string "maybe_vex")
(const_string "sselog1")
]
(const_string "ssemov")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "12,16")
+ (const_string "sselogic")
+ (const_string "*")))
(set (attr "modrm")
(if_then_else (eq_attr "alternative" "11")
(const_string "0")
(const_string "mmxmov")
]
(const_string "ssemov")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "5")
+ (const_string "sselogic")
+ (const_string "*")))
(set (attr "prefix")
(if_then_else (eq_attr "type" "sselog1,ssemov")
(const_string "maybe_vex")
(const_string "mskmov")
]
(const_string "imovx")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "10,11")
+ (const_string "vpmovx")
+ (const_string "*")))
(set (attr "prefix_extra")
(if_then_else (eq_attr "alternative" "10,11")
(const_string "1")
(if_then_else (eq_attr "prefix_0f" "0")
(const_string "double")
(const_string "direct")))
+ (set (attr "c86_decode")
+ (if_then_else (eq_attr "prefix_0f" "0")
+ (const_string "double")
+ (const_string "direct")))
(set (attr "modrm")
(if_then_else (eq_attr "prefix_0f" "0")
(const_string "0")
[(set_attr "type" "fmov")
(set_attr "mode" "<MODE>")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "fp_int_src" "true")])
(define_insn "float<SWI48x:mode>xf2"
[(set_attr "type" "fmov")
(set_attr "mode" "XF")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "fp_int_src" "true")])
(define_expand "float<SWI48x:mode><MODEF:mode>2"
(set_attr "amdfam10_decode" "*,vector,double")
(set_attr "bdver1_decode" "*,double,direct")
(set_attr "znver1_decode" "double,*,*")
+ (set_attr "c86_decode" "double,*,*")
(set_attr "fp_int_src" "true")
(set (attr "enabled")
(if_then_else
[(set_attr "type" "fmov")
(set_attr "mode" "<MODEF:MODE>")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "fp_int_src" "true")])
;; Try TARGET_USE_VECTOR_CONVERTS, but not so hard as to require extra memory
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "DI")])
;; Turn *anddi_1 into *andsi_1_zext if possible.
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "DI")])
(define_insn_and_split "*xordi_1_btc"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "DI")])
;; Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask)
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "<MODE>")])
;; Avoid useless masking of count operand.
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "<MODE>")])
;; Avoid useless masking of count operand.
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "DI")])
(define_insn "*btrq_imm"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "DI")])
(define_insn "*btcq_imm"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "DI")])
;; Allow Nocona to avoid these instructions if a register is available.
(set_attr "prefix_0f" "1")
(set_attr "prefix_rep" "1")
(set_attr "btver2_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "<MODE>")])
; False dependency happens when destination is only updated by tzcnt,
(set_attr "prefix_0f" "1")
(set_attr "prefix_rep" "1")
(set_attr "btver2_decode" "double")
+ (set_attr "c86_decode" "double")
(set_attr "mode" "<MODE>")])
(define_insn "*bsf<mode>_1"
(set_attr "prefix_0f" "1")
(set_attr "btver2_decode" "double")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "<MODE>")])
(define_insn_and_split "ctz<mode>2"
gcc_unreachable ();
}
[(set_attr "type" "alu1")
+ (set_attr "c86_decode" "double")
(set_attr "prefix_0f" "1")
(set_attr "prefix_rep" "1")
(set_attr "mode" "<MODE>")])
(clobber (reg:CC FLAGS_REG))])]
"ix86_expand_clear (operands[0]);"
[(set_attr "type" "alu1")
+ (set_attr "c86_decode" "double")
(set_attr "prefix_0f" "1")
(set_attr "prefix_rep" "1")
(set_attr "mode" "SI")])
"TARGET_BMI && TARGET_64BIT"
"tzcnt{l}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "alu1")
+ (set_attr "c86_decode" "double")
(set_attr "prefix_0f" "1")
(set_attr "prefix_rep" "1")
(set_attr "mode" "SI")])
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "DI")])
(define_insn "bsr_rex64_1"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "DI")])
(define_insn "bsr_rex64_1_zext"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "DI")])
(define_insn "bsr"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "SI")])
(define_insn "bsr_1"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "SI")])
(define_insn "bsr_zext_1"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "SI")])
; As bsr is undefined behavior on zero and for other input
(set_attr "pent_pair" "np,*,*")
(set_attr "athlon_decode" "vector,*,*")
(set_attr "amdfam10_decode" "double,*,*")
+ (set_attr "c86_decode" "vector,*,*")
(set_attr "bdver1_decode" "double,*,*")
(set_attr "mode" "QI,HI,HI")])
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "double")
+ (set_attr "c86_decode" "vector")
(set_attr "bdver1_decode" "double")
(set_attr "mode" "QI")])
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "double")
+ (set_attr "c86_decode" "vector")
(set_attr "bdver1_decode" "double")
(set_attr "mode" "QI")])
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
(set_attr "athlon_decode" "direct")
+ (set_attr "c86_attr" "sqrt")
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "direct")])
"fprem"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "fmodxf3"
"fprem1"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "remainderxf3"
"f<sincos>"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "<sincos><mode>2"
"fsincos"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "sincos<mode>3"
"fptan"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "tanxf2"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "atan2<mode>3"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "logxf2"
"fyl2xp1"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "log1pxf2"
"fxtract"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "logbxf2"
"f2xm1"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_insn "fscalexf4_i387"
"fscale"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "expNcorexf3"
"frndint"
[(set_attr "type" "fpspc")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "XF")])
(define_expand "rinthf2"
v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "prefix" "orig,vex")
+ (set_attr "c86_attr" "maxmin")
(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
v<ieee_maxmin><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "prefix" "orig,maybe_evex")
+ (set_attr "c86_attr" "maxmin")
(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
[(set_attr "isa" "*,x64")
(set_attr "mmx_isa" "native,*")
(set_attr "type" "mmxmov,ssemov")
+ (set_attr "c86_attr" "movnt")
(set_attr "mode" "DI")])
(define_expand "movq_<mode>_to_sse"
vblendps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blend")
(set_attr "length_immediate" "1")
(set_attr "prefix_data16" "1,1,*")
(set_attr "prefix_extra" "1")
vblendvps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blendv")
(set_attr "length_immediate" "1")
(set_attr "prefix_data16" "1,1,*")
(set_attr "prefix_extra" "1")
[(set_attr "isa" "*,sse2_noavx,avx")
(set_attr "mmx_isa" "native,*,*")
(set_attr "type" "mmxmul,sseiadd,sseiadd")
+ (set_attr "c86_attr" "madd")
(set_attr "mode" "DI,TI,TI")])
(define_expand "mmx_pmulhrwv4hi3"
vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blendv")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,orig,vex")
vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blendv")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,orig,vex")
"%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
"%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
"%vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
"%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
(set_attr "addr" "gpr16,*")
(set_attr "prefix_extra" "1")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insr")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
[(set_attr "isa" "*,sse2_noavx,avx,sse4")
(set_attr "mmx_isa" "native,*,*,*")
(set_attr "type" "mmxcvt,sselog,sselog,sselog")
+ (set_attr "c86_attr" "insr")
(set_attr "length_immediate" "1")
(set_attr "mode" "DI,TI,TI,TI")])
}
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insr")
(set_attr "addr" "gpr16,*")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "addr" "*,*,gpr16,*")
(set_attr "mmx_isa" "native,*,*,*")
(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex")
(set_attr "mode" "DI,TI,TI,TI")])
(set_attr "addr" "*,*,gpr16,*,*,*")
(set_attr "mmx_isa" "native,*,*,*,*,*")
(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,sseishft1,sseishft1")
+ (set_attr "c86_attr" "extr,extr,extr,extr,*,*")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex,orig,maybe_evex")
(set_attr "mode" "DI,TI,TI,TI,TI,TI")])
[(set_attr "isa" "*,sse2")
(set_attr "mmx_isa" "native,*")
(set_attr "type" "mmxcvt,sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,maybe_vex")
(set_attr "mode" "DI,TI")])
[(set_attr "isa" "noavx,noavx,avx,avx")
(set_attr "addr" "*,gpr16,*,*")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
"%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blend")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,orig,vex")
vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blend")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,orig,vex")
(const_string "*")))
(set_attr "mmx_isa" "native,*,*,*,*,native,*,*")
(set_attr "type" "mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
+ (set_attr "c86_attr" "*,extr,extr,*,*,*,*,*")
(set (attr "length_immediate")
(if_then_else (eq_attr "alternative" "1,2,3,4")
(const_string "1")
"%vpextrd\t{$1, %1, %k0|%k0, %1, 1}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
}
[(set_attr "isa" "noavx,avx,sse4")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insr")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
[(set_attr "isa" "noavx,avx")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insr")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex")
[(set_attr "isa" "*,sse4_noavx,avx")
(set_attr "addr" "*,gpr16,*")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
[(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
(set_attr "addr" "*,gpr16,*,*,*")
(set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
+ (set_attr "c86_attr" "extr,extr,extr,*,*")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex,orig,maybe_evex,orig,maybe_evex")
(set_attr "mode" "TI")])
"TARGET_SSE2"
"%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
[(set_attr "isa" "noavx,noavx,avx,avx")
(set_attr "addr" "*,gpr16,*,*")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
"%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
[(set_attr "isa" "*,sse2_noavx,avx")
(set_attr "mmx_isa" "native,*,*")
(set_attr "type" "mmxshft,sseiadd,sseiadd")
+ (set_attr "c86_attr" "sadbw")
(set_attr "mode" "DI,TI,TI")])
(define_expand "reduc_<code>_scal_<mode>"
"maskmovq\t{%2, %1|%1, %2}"
[(set_attr "type" "mmxcvt")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "DI")])
(define_int_iterator EMMS
}
}
[(set_attr "type" "ssemov")
+ (set (attr "c86_attr")
+ (if_then_else (and (match_test "REG_P (operands[1])")
+ (match_test "REGNO (operands[1]) != REGNO (operands[0])"))
+ (const_string "blend")
+ (const_string "*")))
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
vmovdqu<ssescalarsize>\t{%2, %0%{%3%}%N1|%0%{%3%}%N1, %2}
vpblendm<sseintmodesuffix>\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "*,blend")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_SSE2"
"movnti\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set_attr "prefix_data16" "0")
(set_attr "mode" "<MODE>")])
"TARGET_SSE"
"%vmovnt<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")])
(match_test "TARGET_AVX")
(const_string "*")
(const_string "1")))
+ (set_attr "c86_attr" "movnt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<sseinsnmode>")])
"ktest<mskmodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "mode" "<MODE>")
(set_attr "type" "msklog")
+ (set_attr "c86_decode" "vector")
(set_attr "prefix" "vex")])
(define_insn "*kortest<mode>"
"kortest<mskmodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "mode" "<MODE>")
(set_attr "type" "msklog")
+ (set_attr "c86_decode" "vector")
(set_attr "prefix" "vex")])
(define_insn "kortest<mode>_ccc"
(set_attr "addr" "*,gpr16")
(set_attr "atom_sse_attr" "rcp")
(set_attr "btver2_sse_attr" "rcp")
+ (set_attr "c86_attr" "rcp")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")])
(set_attr "addr" "*,gpr16")
(set_attr "atom_sse_attr" "rcp")
(set_attr "btver2_sse_attr" "rcp")
+ (set_attr "c86_attr" "rcp")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "SF")])
(set_attr "addr" "*,gpr16")
(set_attr "atom_sse_attr" "rcp")
(set_attr "btver2_sse_attr" "rcp")
+ (set_attr "c86_attr" "rcp")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "SF")])
"TARGET_AVX512F"
"vrcp14<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "sse")
+ (set_attr "c86_attr" "rcp")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX512F"
"vrcp14<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %<iptr>1}"
[(set_attr "type" "sse")
+ (set_attr "c86_attr" "rcp")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX512F"
"vrcp14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}"
[(set_attr "type" "sse")
+ (set_attr "c86_attr" "rcp")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(set_attr "type" "sse")
(set_attr "atom_sse_attr" "sqrt")
(set_attr "btver2_sse_attr" "sqrt")
+ (set_attr "c86_attr" "sqrt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")])
(set_attr "atom_sse_attr" "sqrt")
(set_attr "prefix" "<round_scalar_prefix>")
(set_attr "btver2_sse_attr" "sqrt")
+ (set_attr "c86_attr" "sqrt")
(set_attr "mode" "<ssescalarmode>")])
(define_insn "*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>"
(set_attr "atom_sse_attr" "sqrt")
(set_attr "prefix" "<round_scalar_prefix>")
(set_attr "btver2_sse_attr" "sqrt")
+ (set_attr "c86_attr" "sqrt")
(set_attr "mode" "<ssescalarmode>")])
(define_expand "rsqrt<mode>2"
"TARGET_AVX512F"
"vrsqrt14<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "sse")
+ (set_attr "c86_attr" "rcp")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX512F"
"vrsqrt14<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %<iptr>1}"
[(set_attr "type" "sse")
+ (set_attr "c86_attr" "rcp")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX512F"
"vrsqrt14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}"
[(set_attr "type" "sse")
+ (set_attr "c86_attr" "rcp")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd")
(set_attr "btver2_sse_attr" "maxmin")
+ (set_attr "c86_attr" "maxmin")
(set_attr "prefix" "<mask_prefix3>")
(set_attr "mode" "<MODE>")])
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd")
(set_attr "btver2_sse_attr" "maxmin")
+ (set_attr "c86_attr" "maxmin")
(set_attr "prefix" "<mask_prefix3>")
(set_attr "mode" "<MODE>")])
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd")
(set_attr "btver2_sse_attr" "maxmin")
+ (set_attr "c86_attr" "maxmin")
(set (attr "prefix")
(cond [(eq_attr "alternative" "0")
(const_string "orig")
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sse")
(set_attr "btver2_sse_attr" "maxmin")
+ (set_attr "c86_attr" "maxmin")
(set_attr "prefix" "<round_saeonly_scalar_prefix>")
(set_attr "mode" "<ssescalarmode>")])
"TARGET_AVX"
"vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "addr" "gpr16")
(set_attr "prefix" "vex")
(set_attr "mode" "V4DF")])
[(set_attr "isa" "noavx,avx")
(set_attr "addr" "*,gpr16")
(set_attr "type" "sseadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V2DF")])
vhsubpd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "addr" "*,gpr16")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V2DF")])
vhaddpd\t{%1, %1, %0|%0, %1, %1}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V2DF")])
vhsubpd\t{%1, %1, %0|%0, %1, %1}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V2DF")])
"TARGET_AVX"
"vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "addr" "gpr16")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "addr" "*,gpr16")
(set_attr "atom_unit" "complex")
(set_attr "prefix" "orig,vex")
"TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))"
"vreduce<ssemodesuffix>\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}"
[(set_attr "type" "sse")
+ (set_attr "c86_attr" "aes")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))"
"vreduce<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}"
[(set_attr "type" "sse")
+ (set_attr "c86_attr" "aes")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
[(set_attr "type" "ssecmp")
+ (set_attr "c86_attr" "*,ptest")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
[(set_attr "type" "ssecmp")
+ (set_attr "c86_attr" "*,ptest")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
[(set_attr "isa" "noavx,avx_noavx512f,avx512dq,avx512f")
(set_attr "addr" "*,gpr16,*,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set_attr "prefix" "orig,maybe_vex,evex,evex")
(set (attr "mode")
(cond [(and (match_test "<mask_applied>")
return "";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set_attr "prefix" "evex")
(set (attr "mode")
(if_then_else (match_test "TARGET_AVX512DQ")
}
[(set_attr "isa" "noavx,avx,avx512dq,avx512f")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set_attr "prefix" "orig,maybe_evex,evex,evex")
(set (attr "mode")
(cond [(and (match_test "<mask_applied>")
return "";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set_attr "prefix" "evex")
(set (attr "mode")
(if_then_else (match_test "TARGET_AVX512DQ")
}
[(set_attr "isa" "noavx,avx,avx512vl,avx512f")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set_attr "prefix" "orig,vex,evex,evex")
(set (attr "mode")
(cond [(eq_attr "alternative" "2")
}
[(set_attr "isa" "noavx,avx,avx512vl,avx512f")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set_attr "prefix" "orig,vex,evex,evex")
(set (attr "mode")
(cond [(eq_attr "alternative" "2")
}
[(set_attr "isa" "noavx,avx,avx512vl,avx512f")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set (attr "prefix_data16")
(if_then_else
(and (eq_attr "alternative" "0")
(set_attr "bdver1_decode" "double,direct,*")
(set_attr "btver2_decode" "double,double,double")
(set_attr "znver1_decode" "double,double,double")
+ (set_attr "c86_decode" "double,double,double")
(set (attr "length_vex")
(if_then_else
(and (match_test "<MODE>mode == DImode")
(set_attr "bdver1_decode" "double,direct,*")
(set_attr "btver2_decode" "double,double,double")
(set_attr "znver1_decode" "double,double,double")
+ (set_attr "c86_decode" "double,double,double")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "DF")])
(const_string "ssemov2")
]
(const_string "ssemov")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "9,10,11")
+ (const_string "insr")
+ (const_string "*")))
(set (attr "addr")
(if_then_else (eq_attr "alternative" "9,10")
(const_string "gpr16")
(if_then_else (eq_attr "alternative" "0,1,2,3,6,7,10")
(const_string "ssemov")
(const_string "sselog")))
+ (set (attr "c86_attr")
+ (cond [(eq_attr "alternative" "6,7,10")
+ (const_string "blend")
+ (eq_attr "alternative" "4,5,8,9,11,12")
+ (const_string "insr")
+ ]
+ (const_string "*")))
(set (attr "prefix_data16")
(if_then_else (eq_attr "alternative" "4,5")
(const_string "1")
[(set_attr "isa" "noavx,noavx,avx,noavx,avx")
(set_attr "addr" "gpr16,gpr16,*,*,*")
(set_attr "type" "sselog,sselog,sselog,*,*")
+ (set_attr "c86_attr" "extr,extr,extr,*,*")
(set_attr "prefix_data16" "1,1,1,*,*")
(set_attr "prefix_extra" "1,1,1,*,*")
(set_attr "length_immediate" "1,1,1,*,*")
[(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
(set_attr "addr" "*,gpr16,*,*,*")
(set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
+ (set_attr "c86_attr" "extr,extr,extr,other,other")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "TI")])
"TARGET_AVX512F"
"valign<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}";
[(set_attr "prefix" "evex")
+ (set_attr "c86_attr" "shufx")
(set_attr "mode" "<sseinsnmode>")])
(define_mode_attr vec_extract_imm_predicate
"TARGET_AVX512BW && <mask_mode512bit_condition>"
"vpmaddwd\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}";
[(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "madd")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
"TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "madd")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "madd")
(set_attr "atom_unit" "simul")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix" "orig,vex")
"TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "maxmin")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
"TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "maxmin")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512BW && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "maxmin")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "maxmin")
(set_attr "prefix_extra" "1")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "prefix" "orig,orig,vex")
vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "maxmin")
(set_attr "addr" "gpr16,*")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "maxmin")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "prefix_extra" "1,1,*")
(set_attr "prefix" "orig,orig,vex")
[(set_attr "isa" "noavx,avx")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "maxmin")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
[(set_attr "isa" "noavx,avx_noavx512f,avx512f,*,*")
(set_attr "addr" "*,gpr16,*,*,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set (attr "prefix_data16")
(if_then_else
(and (eq_attr "alternative" "0")
"TARGET_AVX512F"
"vpandn<ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}";
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
[(set_attr "isa" "noavx,avx_noavx512f,avx512f")
(set_attr "addr" "*,gpr16,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set (attr "prefix_data16")
(if_then_else
(and (eq_attr "alternative" "0")
[(set_attr "isa" "noavx,avx_noavx512f,avx512f")
(set_attr "addr" "*,gpr16,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set (attr "prefix_data16")
(if_then_else
(and (eq_attr "alternative" "0")
(set_attr "prefix" "orig,vex,evex")
(set_attr "prefix_data16" "1,*,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "sselogic")
(set_attr "mode" "TI")])
(define_expand "one_cmplv1ti2"
}
[(set_attr "isa" "noavx,noavx,avx,avx,<pinsr_evex_isa>,<pinsr_evex_isa>,avx2")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insr")
(set (attr "addr")
(if_then_else (eq_attr "alternative" "0,1")
(const_string "gpr16")
}
}
[(set_attr "type" "sselog,ssemov,ssemov")
+ (set_attr "c86_attr" "insertx,*,*")
(set_attr "length_immediate" "1,0,0")
(set_attr "prefix" "evex,vex,evex")
(set_attr "mode" "<sseinsnmode>,<ssequarterinsnmode>,<ssequarterinsnmode>")])
return "vinsert<shuffletype><extract_suf>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512DQ"
"vinsert<shuffletype>32x8\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512DQ"
"vinsert<shuffletype>32x8\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512F"
"vinsert<shuffletype>64x4\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
"TARGET_AVX512F"
"vinsert<shuffletype>64x4\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
return "vshuf<shuffletype>64x2\t{%3, %2, %1, %0<mask_operand7>|%0<mask_operand7>, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "shufx")
(set_attr "addr" "gpr16,*")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
return "vshuf<shuffletype>64x2\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "shufx")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
return "vshuf<shuffletype>64x2\t{%2, %1, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %1, %2}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "shufx")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
return "vshuf<shuffletype>32x4\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "shufx")
(set_attr "addr" "gpr16,*")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
return "vshuf<shuffletype>32x4\t{%3, %2, %1, %0<mask_operand19>|%0<mask_operand19>, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "shufx")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
return "vshuf<shuffletype>32x4\t{%2, %1, %1, %0<mask_operand18>|%0<mask_operand18>, %1, %1, %2}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "shufx")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
[(set_attr "isa" "sse2_noavx,avx,sse4_noavx,avx")
(set_attr "addr" "*,*,gpr16,*")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set (attr "prefix_extra")
(if_then_else
(eq (const_string "<MODE>mode") (const_string "V8HImode"))
"%vpextr<PEXTR_MODE12:ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set (attr "prefix_extra")
(if_then_else
(eq (const_string "<PEXTR_MODE12:MODE>mode") (const_string "V8HImode"))
"%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
}
[(set_attr "isa" "noavx,avx,avx512dq,noavx,noavx,avx")
(set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1,sseishft1")
+ (set_attr "c86_attr" "extr,extr,*,*,*,*")
(set (attr "addr")
(if_then_else (eq_attr "alternative" "0")
(const_string "gpr16")
"%vpextrd\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "isa" "noavx,avx,avx512dq")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "extr")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(const_string "imov")
]
(const_string "sselog1")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "0,1,2")
+ (const_string "extr")
+ (const_string "other")))
(set (attr "addr")
(if_then_else (eq_attr "alternative" "0")
(const_string "gpr16")
(const_string "mmxmov")
]
(const_string "sselog")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "0,1,2,3")
+ (const_string "insr")
+ (const_string "other")))
(set (attr "addr")
(if_then_else (eq_attr "alternative" "0,1")
(const_string "gpr16")
(eq_attr "alternative" "0,1,2,3,4,5")
(const_string "sselog")
(const_string "ssemov2")))
+ (set (attr "c86_attr")
+ (if_then_else (eq_attr "alternative" "0,1,2,3")
+ (const_string "insr")
+ (const_string "other")))
(set (attr "addr")
(if_then_else (eq_attr "alternative" "0,1")
(const_string "gpr16")
vpavg<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "avg")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix" "orig,<mask_prefix>")
(set_attr "mode" "<sseinsnmode>")])
vpsadbw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "sadbw")
(set_attr "atom_unit" "simul")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix" "orig,maybe_evex")
"%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
"%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
"%vpmovmskb\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set (attr "prefix_data16")
(if_then_else
(match_test "TARGET_AVX")
"%vpmovmskb\t{%1, %k0|%k0, %1}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set (attr "prefix_data16")
(if_then_else
(match_test "TARGET_AVX")
"%vpmovmskb\t{%1, %k0|%k0, %1}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set (attr "prefix_data16")
(if_then_else
(match_test "TARGET_AVX")
return "%vmaskmovdqu\t{%2, %1|%1, %2}";
}
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blend")
(set_attr "prefix_data16" "1")
(set (attr "length_address")
(symbol_ref ("Pmode != word_mode")))
(symbol_ref ("3 + REX_SSE_REGNO_P (REGNO (operands[2]))")))
(set_attr "prefix" "maybe_vex")
(set_attr "znver1_decode" "vector")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "TI")])
(define_insn "sse_ldmxcsr"
"TARGET_AVX2"
"vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "addr" "gpr16")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
}
[(set_attr "mmx_isa" "native,sse_noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
"TARGET_AVX2"
"vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "addr" "gpr16")
(set_attr "atom_unit" "complex")
(set_attr "prefix_data16" "1,*")
}
[(set_attr "mmx_isa" "native,sse_noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "hplus")
(set_attr "addr" "gpr16")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
"TARGET_AVX2"
"vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "madd")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
"TARGET_AVX512BW"
"vpmaddubsw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}";
[(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "madd")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
[(set_attr "isa" "noavx,avx")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "madd")
(set_attr "atom_unit" "simul")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
[(set_attr "isa" "*,noavx,avx")
(set_attr "mmx_isa" "native,*,*")
(set_attr "type" "sseiadd")
+ (set_attr "c86_attr" "madd")
(set_attr "atom_unit" "simul")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
vpsign<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "sign")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
[(set_attr "isa" "*,noavx,avx")
(set_attr "mmx_isa" "native,*,*")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "sign")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI,TI,TI")])
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
+ (set_attr "c86_attr" "abs")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "abs<mode>2_mask"
"TARGET_AVX512F"
"vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "abs")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512BW"
"vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "abs")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_SSE4A"
"movnt<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set_attr "mode" "<MODE>")])
(define_insn "sse4a_vmmovnt<mode>"
"TARGET_SSE4A"
"movnt<ssescalarmodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set_attr "mode" "<ssescalarmode>")])
(define_insn "sse4a_extrqi"
vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blend")
(set_attr "addr" "gpr16")
(set_attr "length_immediate" "1")
(set_attr "prefix_data16" "1,1,*")
vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blendv")
(set_attr "addr" "gpr16")
(set_attr "length_immediate" "1")
(set_attr "prefix_data16" "1,1,*")
}
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blendv")
(set_attr "length_immediate" "1")
(set_attr "prefix_data16" "1,1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "btver2_decode" "vector,vector,vector")
(set_attr "znver1_decode" "vector,vector,vector")
+ (set_attr "c86_decode" "vector,vector,vector")
(set_attr "mode" "<MODE>")])
;; Mode attribute used by `vmovntdqa' pattern
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "movnt")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
(set_attr "prefix" "orig,orig,vex")
(set_attr "btver2_decode" "vector,vector,vector")
(set_attr "znver1_decode" "vector,vector,vector")
+ (set_attr "c86_decode" "vector,vector,vector")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "avx10_2_mpsadbw<mask_name>"
vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blendv")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "*,*,1")
vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blend")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
return "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blend")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
"TARGET_AVX2"
"vpblendd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "blend")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
"TARGET_AVX2 && <mask_avx512bw_condition> && <mask_avx512vl_condition>"
"vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
"TARGET_AVX512BW"
"vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
"%vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
"TARGET_AVX512F"
"vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
"TARGET_AVX2 && <mask_avx512vl_condition>"
"vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
"TARGET_AVX2 && <mask_avx512vl_condition>"
"%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
"%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
"TARGET_AVX512F"
"vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
"TARGET_AVX2 && <mask_avx512vl_condition>"
"vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
"%vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
"TARGET_AVX512F"
"vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
"TARGET_AVX512F"
"vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
"TARGET_AVX2 && <mask_avx512vl_condition>"
"vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
"TARGET_AVX2 && <mask_avx512vl_condition>"
"vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
"%vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
[(set_attr "isa" "noavx,avx")
(set_attr "addr" "gpr16,*")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "TI")])
"TARGET_AVX512F"
"vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
"TARGET_AVX2 && <mask_avx512vl_condition>"
"vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
"TARGET_AVX2 && <mask_avx512vl_condition>"
"vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
"%vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
"TARGET_AVX512F"
"vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
"TARGET_AVX2 && <mask_avx512vl_condition>"
"vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix" "maybe_evex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "OI")])
"%vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "vpmovx")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "TI")])
}
[(set_attr "isa" "noavx,noavx,noavx512f,avx512f")
(set_attr "type" "ssecvt")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16,gpr16,gpr16,*")
(set_attr "length_immediate" "1")
(set_attr "prefix_data16" "1,1,*,*")
}
[(set_attr "isa" "noavx,noavx,noavx512f,avx512f")
(set_attr "type" "ssecvt")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16,gpr16,gpr16,*")
(set_attr "length_immediate" "1")
(set_attr "prefix_data16" "1,1,*,*")
"TARGET_SSE4_2"
"%vpcmpestri\t{%5, %3, %1|%1, %3, %5}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "cmpestr")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
"TARGET_SSE4_2"
"%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "cmpestr")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
%vpcmpestri\t{%6, %4, %2|%2, %4, %6}
%vpcmpestri\t{%6, %4, %2|%2, %4, %6}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "cmpestr")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
"TARGET_SSE4_2"
"%vpcmpistri\t{%3, %2, %1|%1, %2, %3}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "cmpestr")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
"TARGET_SSE4_2"
"%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "cmpestr")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
%vpcmpistri\t{%4, %3, %2|%2, %3, %4}
%vpcmpistri\t{%4, %3, %2|%2, %3, %4}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "cmpestr")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
"TARGET_XOP"
"vphadd<u>bw\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "vex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
"TARGET_XOP"
"vphadd<u>bd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "vex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
"TARGET_XOP"
"vphadd<u>bq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "vex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
"TARGET_XOP"
"vphadd<u>wd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "vex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
"TARGET_XOP"
"vphadd<u>wq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "vex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
"TARGET_XOP"
"vphadd<u>dq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "vex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
"TARGET_XOP"
"vphsubbw\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "vex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
"TARGET_XOP"
"vphsubwd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "vex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
"TARGET_XOP"
"vphsubdq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseiadd1")
+ (set_attr "c86_attr" "hplus")
(set_attr "prefix" "vex")
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
vaesenc\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx,vaes_avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
vaesenclast\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx,vaes_avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
vaesdec\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx,vaes_avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
[(set_attr "isa" "noavx,avx,vaes_avx512vl")
(set_attr "addr" "gpr16,gpr16,*")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "btver2_decode" "double,double,double")
"TARGET_AES"
"%vaesimc\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
"TARGET_AES"
"%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex,evex")
+ (set_attr "c86_decode" "*,vector,vector")
(set_attr "mode" "TI")])
(define_expand "avx_vzeroall"
return "vperm<ssemodesuffix>\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "perm")
(set_attr "prefix" "<mask_prefix2>")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512VBMI && <mask_mode512bit_condition>"
"vperm<ssemodesuffix>\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "perm")
(set_attr "prefix" "<mask_prefix2>")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512BW && <mask_mode512bit_condition>"
"vpermw\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "perm")
(set_attr "prefix" "<mask_prefix2>")
(set_attr "mode" "<sseinsnmode>")])
return "vperm<ssemodesuffix>\t{%2, %1, %0<mask_operand6>|%0<mask_operand6>, %1, %2}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "perm")
(set_attr "prefix" "<mask_prefix2>")
(set_attr "mode" "<sseinsnmode>")])
return "vperm<ssemodesuffix>\t{%2, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %2}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "perm")
(set_attr "prefix" "<mask_prefix2>")
(set_attr "mode" "<sseinsnmode>")])
vshuf<shuffletype>32x4\t{$0x0, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x0}
vbroadcast<shuffletype>32x4\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "shufx,*")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
vshuf<shuffletype>64x2\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}
vbroadcast<shuffletype>64x4\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "shufx,*")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
vinsert<shuffletype>32x4\t{$1, %1, %0, %0|%0, %0, %1, 1}"
[(set_attr "isa" "noavx512vl,*,*,avx512dq,avx512dq,avx512vl,avx512vl")
(set_attr "type" "ssemov,sselog1,sselog1,ssemov,sselog1,ssemov,sselog1")
+ (set_attr "c86_attr" "*,insertx,*,*,insertx,*,insertx")
(set (attr "addr")
(if_then_else (eq_attr "alternative" "0")
(const_string "gpr16")
vshuf<shuffletype>32x4\t{$0x0, %t1, %t1, %0<mask_operand2>|%0<mask_operand2>, %t1, %t1, 0x0}
vbroadcast<shuffletype>32x4\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "shufx,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
vshuf<shuffletype>32x4\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}
vbroadcast<shuffletype>32x8\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "shufx,*")
(set_attr "length_immediate" "1,*")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
vshuf<shuffletype>64x2\t{$0x0, %<xtg_mode>1, %<xtg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<xtg_mode>1, %<xtg_mode>1, 0x0}
vbroadcast<shuffletype>64x2\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "shufx,*")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512F"
"vpermi2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "perm2")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512F"
"vpermi2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "perm2")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
vpermt2<ssemodesuffix>\t{%3, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %3}
vpermi2<ssemodesuffix>\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "perm2")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512F"
"vpermt2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}"
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "perm2")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
return "vperm2<i128>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex,evex")
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16,*")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex,evex")
vinserti32x4\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "addr" "gpr16,*")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
[(set_attr "isa" "noavx512vl,avx512vl")
(set_attr "addr" "gpr16")
(set_attr "type" "sselog")
+ (set_attr "c86_attr" "insertx")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex,evex")
return "vmaskmov<ssefltmodesuffix>\t{%1, %2, %0|%0, %2, %1}";
}
[(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "blend")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
return "vmaskmov<ssefltmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "blend")
(set_attr "addr" "gpr16")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
[(set_attr "isa" "noavx512f,avx512f,*,*")
(set_attr "addr" "gpr16,*,*,*")
(set_attr "type" "sselog,sselog,ssemov,ssemov")
+ (set_attr "c86_attr" "insertx,insertx,*,*")
(set_attr "prefix_extra" "1,1,*,*")
(set_attr "length_immediate" "1,1,*,*")
(set_attr "prefix" "maybe_evex")
"TARGET_AVX512F"
"v<sseintprefix>compress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "compress")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512VBMI2"
"vpcompress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "compress")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512F"
"v<sseintprefix>compress<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "compress")
(set_attr "prefix" "evex")
(set_attr "memory" "store")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512VBMI2"
"vpcompress<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "compress")
(set_attr "prefix" "evex")
(set_attr "memory" "store")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512F"
"v<sseintprefix>expand<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "expand")
(set_attr "prefix" "evex")
(set_attr "memory" "none,load")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512VBMI2"
"v<sseintprefix>expand<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "c86_attr" "expand")
(set_attr "prefix" "evex")
(set_attr "memory" "none,load")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512BW"
"vdbpsadbw\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"
[(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "sadbw")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512CD"
"vplzcnt<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "sse")
+ (set_attr "c86_attr" "abs")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"vpconflict<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "sse")
(set_attr "prefix" "evex")
+ (set_attr "c86_decode" "vector")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "sha1msg1"
"TARGET_AVX512IFMA"
"vpmadd52<vpmadd52type>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "c86_attr" "madd")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
vpmadd52<vpmadd52type>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "isa" "avxifma,avx512ifmavl")
(set_attr "type" "ssemuladd")
+ (set_attr "c86_attr" "madd")
(set_attr "addr" "gpr16,*")
(set_attr "prefix" "vex,evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512IFMA"
"vpmadd52<vpmadd52type>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "c86_attr" "madd")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
"TARGET_AVX512IFMA"
"vpmadd52<vpmadd52type>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "c86_attr" "madd")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
}
[(set_attr "isa" "avx,vaes_avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16,*")
(set_attr "mode" "TI")])
}
[(set_attr "isa" "avx,vaes_avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16,*")
(set_attr "mode" "TI")])
}
[(set_attr "isa" "avx,vaes_avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16,*")
(set_attr "mode" "TI")])
}
[(set_attr "isa" "avx,vaes_avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "c86_attr" "aes")
(set_attr "addr" "gpr16,*")
(set_attr "mode" "TI")])
COSTS_N_INSNS (2), /* Branch mispredict scale. */
};
+/* C86_4G_M4 has optimized REP instruction for medium sized blocks, but for
+ very small blocks it is better to use loop. For large blocks, libcall
+ can do nontemporary accesses and beat inline considerably. */
+static stringop_algs c86_4g_m4_memcpy[2] = {
+ /* 32-bit tuning. */
+ {libcall, {{6, loop, false},
+ {14, unrolled_loop, false},
+ {-1, libcall, false}}},
+ /* 64-bit tuning. */
+ {libcall, {{16, loop, false},
+ {128, rep_prefix_8_byte, false},
+ {-1, libcall, false}}}};
+static stringop_algs c86_4g_m4_memset[2] = {
+ /* 32-bit tuning. */
+ {libcall, {{8, loop, false},
+ {24, unrolled_loop, false},
+ {128, rep_prefix_4_byte, false},
+ {-1, libcall, false}}},
+ /* 64-bit tuning. */
+ {libcall, {{48, unrolled_loop, false},
+ {128, rep_prefix_8_byte, false},
+ {-1, libcall, false}}}};
+static const
+struct processor_costs c86_4g_m4_cost = {
+ {
+ /* Start of register allocator costs. integer->integer move cost is 2. */
+
+ /* reg-reg moves are done by renaming and thus they are even cheaper than
+ 1 cycle. Because reg-reg move cost is 2 and the following tables
+ correspond to doubles of latencies, we do not model this correctly.
+ It does not seem to make practical difference to bump prices up even
+ more. */
+ 6, /* cost for loading QImode using
+ movzbl. */
+ {6, 6, 6}, /* cost of loading integer registers
+ in QImode, HImode and SImode.
+ Relative to reg-reg move (2). */
+ {8, 8, 8}, /* cost of storing integer
+ registers. */
+ 2, /* cost of reg,reg fld/fst. */
+ {6, 6, 16}, /* cost of loading fp registers
+ in SFmode, DFmode and XFmode. */
+ {8, 8, 16}, /* cost of storing fp registers
+ in SFmode, DFmode and XFmode. */
+ 2, /* cost of moving MMX register. */
+ {6, 6}, /* cost of loading MMX registers
+ in SImode and DImode. */
+ {8, 8}, /* cost of storing MMX registers
+ in SImode and DImode. */
+ 2, 3, 6, /* cost of moving XMM,YMM,ZMM register. */
+ {6, 6, 6, 12, 24}, /* cost of loading SSE registers
+ in 32,64,128,256 and 512-bit. */
+ {8, 8, 8, 16, 32}, /* cost of storing SSE registers
+ in 32,64,128,256 and 512-bit. */
+ 6, 6, /* SSE->integer and integer->SSE moves. */
+ 8, 8, /* mask->integer and integer->mask moves */
+ {6, 6, 6}, /* cost of loading mask register
+ in QImode, HImode, SImode. */
+ {8, 8, 8}, /* cost if storing mask register
+ in QImode, HImode, SImode. */
+ 2, /* cost of moving mask register. */
+ /* End of register allocator costs. */
+ },
+
+ COSTS_N_INSNS (1), /* cost of an add instruction. */
+ COSTS_N_INSNS (1), /* cost of a lea instruction. */
+ COSTS_N_INSNS (1), /* variable shift costs. */
+ COSTS_N_INSNS (1), /* constant shift costs. */
+ {COSTS_N_INSNS (3), /* cost of starting multiply for QI. */
+ COSTS_N_INSNS (3), /* HI. */
+ COSTS_N_INSNS (3), /* SI. */
+ COSTS_N_INSNS (3), /* DI. */
+ COSTS_N_INSNS (3)}, /* other. */
+ 0, /* cost of multiply per each bit
+ set. */
+ /* Depending on parameters, idiv can get faster on HYGON. This is upper
+ bound. */
+ {COSTS_N_INSNS (16), /* cost of a divide/mod for QI. */
+ COSTS_N_INSNS (22), /* HI. */
+ COSTS_N_INSNS (30), /* SI. */
+ COSTS_N_INSNS (45), /* DI. */
+ COSTS_N_INSNS (45)}, /* other. */
+ COSTS_N_INSNS (1), /* cost of movsx. */
+ COSTS_N_INSNS (1), /* cost of movzx. */
+ 8, /* "large" insn. */
+ 9, /* MOVE_RATIO. */
+ 6, /* CLEAR_RATIO */
+ {6, 6, 6}, /* cost of loading integer registers
+ in QImode, HImode and SImode.
+ Relative to reg-reg move (2). */
+ {8, 8, 8}, /* cost of storing integer
+ registers. */
+ {6, 6, 6, 12, 24}, /* cost of loading SSE register
+ in 32bit, 64bit, 128bit, 256bit and 512bit */
+ {8, 8, 8, 16, 32}, /* cost of storing SSE register
+ in 32bit, 64bit, 128bit, 256bit and 512bit */
+ {6, 6, 6, 12, 24}, /* cost of unaligned loads. */
+ {8, 8, 8, 16, 32}, /* cost of unaligned stores. */
+ 2, 3, 6, /* cost of moving XMM,YMM,ZMM register. */
+ 6, /* cost of moving SSE register to integer. */
+ 6, /* cost of moving integer register to SSE. */
+
+ 18, 8, /* Gather load static, per_elt. */
+ 18, 10, /* Gather store static, per_elt. */
+ 32, /* size of l1 cache. */
+ 512, /* size of l2 cache. */
+ 64, /* size of prefetch block. */
+ /* C86_4G_M4 processors never drop prefetches; if they cannot be performed
+ immediately, they are queued. We set number of simultaneous prefetches
+ to a large constant to reflect this (it probably is not a good idea not
+ to limit number of prefetches at all, as their execution also takes some
+ time). */
+ 100, /* number of parallel prefetches. */
+ 3, /* Branch cost. */
+ COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
+ COSTS_N_INSNS (5), /* cost of FMUL instruction. */
+
+ COSTS_N_INSNS (15), /* cost of FDIV instruction. */
+ COSTS_N_INSNS (1), /* cost of FABS instruction. */
+ COSTS_N_INSNS (1), /* cost of FCHS instruction. */
+
+ COSTS_N_INSNS (10), /* cost of FSQRT instruction. */
+
+ COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
+ COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
+ COSTS_N_INSNS (3), /* cost of MULSS instruction. */
+ COSTS_N_INSNS (4), /* cost of MULSD instruction. */
+ COSTS_N_INSNS (5), /* cost of FMA SS instruction. */
+ COSTS_N_INSNS (5), /* cost of FMA SD instruction. */
+ COSTS_N_INSNS (10), /* cost of DIVSS instruction. */
+
+ COSTS_N_INSNS (13), /* cost of DIVSD instruction. */
+ COSTS_N_INSNS (10), /* cost of SQRTSS instruction. */
+ COSTS_N_INSNS (15), /* cost of SQRTSD instruction. */
+
+ COSTS_N_INSNS (4), /* cost of CVTSS2SD etc. */
+ COSTS_N_INSNS (5), /* cost of 256bit VCVTPS2PD etc. */
+ COSTS_N_INSNS (10), /* cost of 512bit VCVTPS2PD etc. */
+ COSTS_N_INSNS (5), /* cost of CVTSI2SS instruction. */
+ COSTS_N_INSNS (5), /* cost of CVT(T)SS2SI instruction. */
+ COSTS_N_INSNS (5), /* cost of CVTPI2PS instruction. */
+ COSTS_N_INSNS (4), /* cost of CVT(T)PS2PI instruction. */
+
+ 4, 4, 3, 6, /* reassoc int, fp, vec_int, vec_fp. */
+ {8, 1, 6}, /* latency times throughput of
+ FMA/DOT_PROD_EXPR/SAD_EXPR,
+ it's used to determine unroll
+ factor in the vectorizer. */
+ 4, /* Limit how much the autovectorizer
+ may unroll a loop. */
+ c86_4g_m4_memcpy,
+ c86_4g_m4_memset,
+ COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
+ COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
+ "16", /* Loop alignment. */
+ "16", /* Jump alignment. */
+ "0:0:8", /* Label alignment. */
+ "16", /* Func alignment. */
+ 4, /* Small unroll limit. */
+ 2, /* Small unroll factor. */
+ COSTS_N_INSNS (2), /* Branch mispredict scale. */
+};
+
+struct processor_costs c86_4g_m6_cost = c86_4g_m4_cost;
+
+struct processor_costs c86_4g_m7_cost = {
+ {
+ /* Start of register allocator costs. integer->integer move cost is 2. */
+
+ /* reg-reg moves are done by renaming and thus they are even cheaper than
+ 1 cycle. Because reg-reg move cost is 2 and following tables correspond
+ to doubles of latencies, we do not model this correctly. It does not
+ seem to make practical difference to bump prices up even more. */
+ 6, /* cost for loading QImode using
+ movzbl. */
+ {6, 6, 6}, /* cost of loading integer registers
+ in QImode, HImode and SImode.
+ Relative to reg-reg move (2). */
+ {8, 8, 8}, /* cost of storing integer
+ registers. */
+ 2, /* cost of reg,reg fld/fst. */
+ {14, 14, 17}, /* cost of loading fp registers
+ in SFmode, DFmode and XFmode. */
+ {12, 12, 16}, /* cost of storing fp registers
+ in SFmode, DFmode and XFmode. */
+ 2, /* cost of moving MMX register. */
+ {6, 6}, /* cost of loading MMX registers
+ in SImode and DImode. */
+ {8, 8}, /* cost of storing MMX registers
+ in SImode and DImode. */
+ 2, 2, 3, /* cost of moving XMM,YMM,ZMM
+ register. */
+ {6, 6, 10, 10, 12}, /* cost of loading SSE registers
+ in 32,64,128,256 and 512-bit. */
+ {8, 8, 8, 12, 12}, /* cost of storing SSE registers
+ in 32,64,128,256 and 512-bit. */
+ 6, 8, /* SSE->integer and integer->SSE
+ moves. */
+ 8, 8, /* mask->integer and integer->mask moves */
+ {6, 6, 6}, /* cost of loading mask register
+ in QImode, HImode, SImode. */
+ {8, 8, 8}, /* cost if storing mask register
+ in QImode, HImode, SImode. */
+ 2, /* cost of moving mask register. */
+ /* End of register allocator costs. */
+ },
+
+ COSTS_N_INSNS (1), /* cost of an add instruction. */
+
+ COSTS_N_INSNS (1), /* cost of a lea instruction. */
+ COSTS_N_INSNS (1), /* variable shift costs. */
+ COSTS_N_INSNS (1), /* constant shift costs. */
+ {COSTS_N_INSNS (3), /* cost of starting multiply for QI. */
+ COSTS_N_INSNS (3), /* HI. */
+ COSTS_N_INSNS (3), /* SI. */
+ COSTS_N_INSNS (3), /* DI. */
+ COSTS_N_INSNS (3)}, /* other. */
+ 0, /* cost of multiply per each bit
+ set. */
+ {COSTS_N_INSNS (15), /* cost of a divide/mod for QI. */
+ COSTS_N_INSNS (17), /* HI. */
+ COSTS_N_INSNS (25), /* SI. */
+ COSTS_N_INSNS (41), /* DI. */
+ COSTS_N_INSNS (41)}, /* other. */
+ COSTS_N_INSNS (1), /* cost of movsx. */
+ COSTS_N_INSNS (1), /* cost of movzx. */
+ 8, /* "large" insn. */
+ 9, /* MOVE_RATIO. */
+ 6, /* CLEAR_RATIO */
+ {6, 6, 6}, /* cost of loading integer registers
+ in QImode, HImode and SImode.
+ Relative to reg-reg move (2). */
+ {8, 8, 8}, /* cost of storing integer
+ registers. */
+ {6, 6, 10, 10, 12}, /* cost of loading SSE registers
+ in 32bit, 64bit, 128bit, 256bit and 512bit */
+ {8, 8, 8, 12, 12}, /* cost of storing SSE register
+ in 32bit, 64bit, 128bit, 256bit and 512bit */
+ {6, 6, 10, 10, 12}, /* cost of unaligned loads. */
+ {8, 8, 8, 12, 12}, /* cost of unaligned stores. */
+ 2, 2, 3, /* cost of moving XMM,YMM,ZMM
+ register. */
+ 6, /* cost of moving SSE register to integer. */
+ 6, /* cost of moving integer register to SSE. */
+
+ 14, 10, /* Gather load static, per_elt. */
+ 14, 20, /* Gather store static, per_elt. */
+ 32, /* size of l1 cache. */
+ 512, /* size of l2 cache. */
+ 64, /* size of prefetch block. */
+
+ 100, /* number of parallel prefetches. */
+ 3, /* Branch cost. */
+ COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
+ COSTS_N_INSNS (5), /* cost of FMUL instruction. */
+
+ COSTS_N_INSNS (15), /* cost of FDIV instruction. */
+ COSTS_N_INSNS (1), /* cost of FABS instruction. */
+ COSTS_N_INSNS (1), /* cost of FCHS instruction. */
+
+ COSTS_N_INSNS (22), /* cost of FSQRT instruction. */
+
+ COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
+ COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
+ COSTS_N_INSNS (3), /* cost of MULSS instruction. */
+ COSTS_N_INSNS (3), /* cost of MULSD instruction. */
+ COSTS_N_INSNS (4), /* cost of FMA SS instruction. */
+ COSTS_N_INSNS (4), /* cost of FMA SD instruction. */
+ COSTS_N_INSNS (13), /* cost of DIVSS instruction. */
+
+ COSTS_N_INSNS (10), /* cost of DIVSD instruction. */
+ COSTS_N_INSNS (14), /* cost of SQRTSS instruction. */
+ COSTS_N_INSNS (20), /* cost of SQRTSD instruction. */
+
+ COSTS_N_INSNS (4), /* cost of CVTSS2SD etc. */
+ COSTS_N_INSNS (5), /* cost of 256bit VCVTPS2PD etc. */
+ COSTS_N_INSNS (10), /* cost of 512bit VCVTPS2PD etc. */
+ COSTS_N_INSNS (5), /* cost of CVTSI2SS instruction. */
+ COSTS_N_INSNS (5), /* cost of CVT(T)SS2SI instruction. */
+ COSTS_N_INSNS (5), /* cost of CVTPI2PS instruction. */
+ COSTS_N_INSNS (4), /* cost of CVT(T)PS2PI instruction. */
+ 4, 4, 3, 6, /* reassoc int, fp, vec_int, vec_fp. */
+ {8, 8, 6}, /* latency times throughput of
+ FMA/DOT_PROD_EXPR/SAD_EXPR,
+ it's used to determine unroll
+ factor in the vectorizer. */
+ 4, /* Limit how much the autovectorizer
+ may unroll a loop. */
+ c86_4g_m4_memcpy,
+ c86_4g_m4_memset,
+ COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
+ COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
+ "16", /* Loop alignment. */
+ "16", /* Jump alignment. */
+ "0:0:8", /* Label alignment. */
+ "16", /* Func alignment. */
+ 4, /* Small unroll limit. */
+ 2, /* Small unroll factor. */
+ COSTS_N_INSNS (2), /* Branch mispredict scale. */
+};
is limits of the decoders. */
case PROCESSOR_ZNVER5:
case PROCESSOR_ZNVER6:
+ case PROCESSOR_C86_4G_M4:
+ case PROCESSOR_C86_4G_M6:
+ case PROCESSOR_C86_4G_M7:
return 4;
case PROCESSOR_ICELAKE_CLIENT:
case PROCESSOR_ZNVER4:
case PROCESSOR_ZNVER5:
case PROCESSOR_ZNVER6:
+ case PROCESSOR_C86_4G_M4:
+ case PROCESSOR_C86_4G_M6:
+ case PROCESSOR_C86_4G_M7:
/* Stack engine allows to execute push&pop instructions in parall. */
if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
&& (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_INTEL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
- | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
+ | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G
| m_GENERIC)
/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2
| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
| m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
- | m_CORE_ATOM | m_GENERIC)
+ | m_CORE_ATOM | m_C86_4G | m_GENERIC)
/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
destinations to be 128bit to allow register renaming on 128bit SSE units,
DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
| m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
- | m_CORE_ATOM | m_GENERIC)
+ | m_CORE_ATOM | m_C86_4G | m_GENERIC)
/* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
partial write to the destination in scalar SSE conversion from FP
"sse_partial_reg_fp_converts_dependency",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
| m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
- | m_GENERIC)
+ | m_C86_4G | m_GENERIC)
/* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
write to the destination in scalar SSE conversion from integer to FP. */
"sse_partial_reg_converts_dependency",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
| m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
- | m_GENERIC)
+ | m_C86_4G | m_GENERIC)
/* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before
several insns to break false dependency on the dest register for GLC
m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_INTEL
| m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
- | m_CORE_AVX2 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
+ | m_CORE_AVX2 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
+ | m_C86_4G | m_GENERIC)
/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
full sized loads. */
DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
| m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE | m_ZHAOXIN
- | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
+ | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
conditional jump instruction for 32 bit TARGET. */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
- m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)
+ m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
conditional jump instruction for TARGET_64BIT. */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
- | m_ZNVER | m_ZHAOXIN | m_GENERIC)
+ | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
subsequent conditional jump instruction when the condition jump
check sign flag (SF) or overflow flag (OF). */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
- | m_ZNVER | m_ZHAOXIN | m_GENERIC)
+ | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
/* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
jump instruction when the alu instruction produces the CCFLAG consumed by
/* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */
DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
- | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
+ | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
/* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
Some chips, like 486 and Pentium works faster with separate load
and push instructions. */
DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
- | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
+ | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G
+ | m_GENERIC)
/* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
over esp subtraction. */
~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
| m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
- | m_GENERIC))
+ | m_C86_4G | m_GENERIC))
/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
will impact LEA instruction selection. */
DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
"misaligned_move_string_pro_epilogues",
m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT
- | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
+ | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
/* X86_TUNE_USE_SAHF: Controls use of SAHF. */
DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER
| m_ZNVER | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
- | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
+ | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL | m_LAKEMONT
| m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS
- | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
+ | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
for bit-manipulation instructions. */
/* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */
DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
- | m_CORE_ATOM | m_GENERIC)
+ | m_CORE_ATOM | m_C86_4G | m_GENERIC)
/* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
| m_SILVERMONT | m_INTEL | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
| m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
- | m_GENERIC))
+ | m_C86_4G | m_GENERIC))
/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
-DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_ZHAOXIN)
+DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_ZHAOXIN
+ | m_C86_4G)
/* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */
DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_INTEL
| m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
| m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_ZHAOXIN
- | m_GENERIC)
+ | m_C86_4G | m_GENERIC)
/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
instead of a sequence loading registers by parts. */
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT
| m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
- | m_CORE_ATOM | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)
+ | m_CORE_ATOM | m_BDVER | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
precision 128bit instructions instead of double where possible. */
DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
- m_BDVER | m_ZNVER)
+ m_BDVER | m_ZNVER | m_C86_4G)
/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */
DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
m_AMD_MULTIPLE | m_ZHAOXIN | m_CORE_ALL | m_TREMONT | m_CORE_HYBRID
- | m_CORE_ATOM | m_GENERIC)
+ | m_CORE_ATOM | m_C86_4G | m_GENERIC)
/* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
xorps/xorpd and other variants. */
DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
- | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
+ | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
+ | m_C86_4G | m_GENERIC)
/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
to SSE registers. If disabled, the moves will be done by storing
elements. */
DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts",
~(m_ZNVER | m_CORE_HYBRID
- | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
+ | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS
+ | m_C86_4G))
/* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
elements. */
DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
- ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))
+ ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))
+
/* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4
elements. */
DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts",
~(m_ZNVER | m_CORE_HYBRID
- | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
+ | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS
+ | m_C86_4G))
/* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
elements. */
DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
- ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))
+ ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))
/* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more
elements. */
DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts",
~(m_ZNVER | m_CORE_HYBRID | m_CORE_ATOM
- | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS))
+ | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS | m_C86_4G))
/* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
elements. */
DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts",
- ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))
+ ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))
/* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
smaller FMA chain. */
DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER
- | m_YONGFENG | m_SHIJIDADAO | m_GENERIC)
+ | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_C86_4G)
/* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
smaller FMA chain. */
DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains",
m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_CORE_HYBRID
| m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
- | m_DIAMONDRAPIDS | m_CORE_ATOM | m_GENERIC)
+ | m_DIAMONDRAPIDS | m_CORE_ATOM | m_GENERIC | m_C86_4G)
/* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or
smaller FMA chain. */
/* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI,
V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */
DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF,
- "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5)
+ "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7)
/*****************************************************************************/
/* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
"avx256_avoid_vec_perm", m_CORE_ATOM)
/* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops. */
-DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4)
+DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4
+ | m_C86_4G_M7)
/* It's better to align MOVE_MAX with prefer_vector_width to reduce
risk of STLF stalls(small store followed by big load.) */
/* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
AVX instructions. */
DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
- m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3)
+ m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3
+ | m_C86_4G_M4 | m_C86_4G_M6)
/* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
AVX instructions. */
DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
- m_ZNVER4 | m_ZNVER5 | m_ZNVER6)
+ m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7)
/* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
vectorized loops. */
/* X86_TUNE_AVX512_MAKED_EPILOGUES: Use two masked vector epilogues
when fit. */
DEF_TUNE (X86_TUNE_AVX512_MASKED_EPILOGUES, "avx512_masked_epilogues",
- m_ZNVER4 | m_ZNVER5)
+ m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7)
/*****************************************************************************/
/*****************************************************************************/
DEF_TUNE (X86_TUNE_SLOW_STC, "slow_stc", m_PENT4)
/* X86_TUNE_USE_RCR: Controls use of rcr 1 instruction instead of shrd. */
-DEF_TUNE (X86_TUNE_USE_RCR, "use_rcr", m_AMD_MULTIPLE)
+DEF_TUNE (X86_TUNE_USE_RCR, "use_rcr", m_AMD_MULTIPLE | m_C86_4G)
@item znver6
AMD Family 1ah Zen version 6.
+
+@item hygonfam18h
+HYGON Family 18h CPU.
+
+@item c86-4g-m4
+HYGON Family 18h model 4 dharma CPU.
+
+@item c86-4g-m6
+HYGON Family 18h model 6 shanghai CPU.
+
+@item c86-4g-m7
+HYGON Family 18h model 7 chengdu CPU.
@end table
Here is an example:
@item geode
AMD Geode embedded processor with MMX and 3DNow!@: instruction set support.
+
+@item c86-4g-m4
+HYGON c86-4g-m4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
+
+@item c86-4g-m6
+HYGON c86-4g-m6 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
+
+@item c86-4g-m7
+HYGON c86-4g-m7 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,
+AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES,
+AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ,
+WBNOINVD instruction set support.
@end table
@opindex mtune
--- /dev/null
+// Test that dispatching can choose the right multiversion
+// for HYGON CPUs with the same internal GCC processor id
+
+// { dg-do run }
+// { dg-require-ifunc "" }
+// { dg-options "-O2" }
+
+#include <assert.h>
+
+int __attribute__ ((target("default")))
+foo ()
+{
+ return 0;
+}
+
+int __attribute__ ((target("arch=c86-4g-m4"))) foo () {
+ return 1;
+}
+
+int __attribute__ ((target("arch=c86-4g-m6"))) foo () {
+ return 2;
+}
+
+int __attribute__ ((target("arch=c86-4g-m7"))) foo () {
+ return 3;
+}
+
+int main ()
+{
+ int val = foo ();
+
+ if (__builtin_cpu_is ("c86-4g-m4"))
+ assert (val == 1);
+ else if (__builtin_cpu_is ("c86-4g-m6"))
+ assert (val == 2);
+ else if (__builtin_cpu_is ("c86-4g-m7"))
+ assert (val == 3);
+ else
+ assert (val == 0);
+
+ return 0;
+}
assert (__builtin_cpu_is ("amd"));
get_amd_cpu (&cpu_model, &cpu_model2, cpu_features2);
break;
+ case VENDOR_HYGON:
+ assert (__builtin_cpu_is ("hygon"));
+ get_hygon_cpu (&cpu_model, &cpu_model2, cpu_features2);
+ break;
default:
break;
}
assert (__builtin_cpu_is ("bdver2") >= 0);
+ assert (__builtin_cpu_is ("c86-4g-m4") >= 0);
+
return 0;
}
extern void test_arch_znver4 (void) __attribute__((__target__("arch=znver4")));
extern void test_arch_znver5 (void) __attribute__((__target__("arch=znver5")));
extern void test_arch_znver6 (void) __attribute__((__target__("arch=znver6")));
+extern void test_arch_c86_4g_m4 (void) __attribute__((__target__("arch=c86-4g-m4")));
+extern void test_arch_c86_4g_m6 (void) __attribute__((__target__("arch=c86-4g-m6")));
+extern void test_arch_c86_4g_m7 (void) __attribute__((__target__("arch=c86-4g-m7")));
extern void test_tune_nocona (void) __attribute__((__target__("tune=nocona")));
extern void test_tune_core2 (void) __attribute__((__target__("tune=core2")));
extern void test_tune_znver4 (void) __attribute__((__target__("tune=znver4")));
extern void test_tune_znver5 (void) __attribute__((__target__("tune=znver5")));
extern void test_tune_znver6 (void) __attribute__((__target__("tune=znver6")));
+extern void test_tune_c86_4g_m4 (void) __attribute__((__target__("tune=c86-4g-m4")));
+extern void test_tune_c86_4g_m6 (void) __attribute__((__target__("tune=c86-4g-m6")));
+extern void test_tune_c86_4g_m7 (void) __attribute__((__target__("tune=c86-4g-m7")));
extern void test_fpmath_sse (void) __attribute__((__target__("sse2,fpmath=sse")));
extern void test_fpmath_387 (void) __attribute__((__target__("sse2,fpmath=387")));
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