drm/amdgpu: Use asic specific pte_addr_mask

For PTE creation use asic specific physical page base address mask

v2: Change variable name from pa_mask to pte_addr_mask

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 291e85e37a6806dc4a118f4f0a97443d7931b99c..821dca9ee18cad0ea42df7ebe9405460b59908b9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -170,7 +170,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
        /*
         * The following is for PTE only. GART does not have PDEs.
        */
-       value = addr & 0x0000FFFFFFFFF000ULL;
+       value = addr & adev->gmc.pte_addr_mask;
        value |= flags;
        writeq(value, ptr + (gpu_page_idx * 8));
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 676e3aaa1f27dfa56e3162d48e2c78f02d262dc0..ddb0d500e0faa2f6eb710c051ac7615fb2ac5822 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -280,6 +280,7 @@ struct amdgpu_gmc {
        u64                     real_vram_size;
        int                     vram_mtrr;
        u64                     mc_mask;
+       uint64_t                pte_addr_mask;
        const struct firmware   *fw;    /* MC firmware */
        uint32_t                fw_version;
        struct amdgpu_irq_src   vm_fault;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 8523833a74fbf455bb6513be5921eb25699c840b..6be2000c82614a5a68d524723659131f58241c7a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -843,6 +843,7 @@ static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
+       adev->gmc.pte_addr_mask = 0x0000FFFFFFFFF000ULL; /* 48 bit PA */
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 41ec28bbff0524e69992ff91304b45dafc4bfbea..8eb9847d9e1e059ed5f5e2d75adf814af00f2219 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -821,6 +821,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
+       adev->gmc.pte_addr_mask = 0x0000FFFFFFFFF000ULL; /* 48 bit PA */
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index 586703ec0dfa0b4dd1500779f4fa2e26d1b6dfb3..82325355f48ac327e0ee422bb4cea3e9a5690c00 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -813,6 +813,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
 {
        int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
        struct amdgpu_device *adev = ip_block->adev;
+       uint64_t pte_addr_mask = 0;
        int i;
 
        adev->mmhub.funcs->init(adev);
@@ -842,6 +843,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
                 * block size 512 (9bit)
                 */
                amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
+               pte_addr_mask = 0x0000FFFFFFFFF000ULL; /* 48 bit PA */
                break;
        case IP_VERSION(12, 1, 0):
                bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
@@ -854,6 +856,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
                 * block size 512 (9bit)
                 */
                amdgpu_vm_adjust_size(adev, 128 * 1024 * 1024, 9, 4, 57);
+               pte_addr_mask = 0x000FFFFFFFFFF000ULL; /* 52 bit PA */
                break;
        default:
                break;
@@ -910,6 +913,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = AMDGPU_GMC_HOLE_MASK;
+       adev->gmc.pte_addr_mask = pte_addr_mask;
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index af6944d2d330d1665bf0fe098a4e6a7f30efb972..a914dd8183b58b26dab50a50bd4ed6704783a91e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -830,6 +830,7 @@ static int gmc_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
        amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
 
        adev->gmc.mc_mask = 0xffffffffffULL;
+       adev->gmc.pte_addr_mask = 0x000000FFFFFFF000ULL;
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 96023b4f5f923ead0715db5a075ce917d1376f6f..98db62cc87186d9b0ada65bd928ac244e3752e1f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1010,6 +1010,7 @@ static int gmc_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
+       adev->gmc.pte_addr_mask = 0x000000FFFFFFF000ULL; /* 40 bit PA */
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index b76fc4441eb7911cec16bcbbcc149fe4af1f8c30..c2a41fa3a396b615900ec13a2c6ab59f350f6357 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1125,6 +1125,7 @@ static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
+       adev->gmc.pte_addr_mask = 0x000000FFFFFFF000ULL; /* 40 bit PA */
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ced0f3941863f52963b49cc25e8f2e86e463dc38..8a5c44810ba1eec04f51bf6b9bee31cba3cd5671 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1983,6 +1983,7 @@ static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
+       adev->gmc.pte_addr_mask = 0x0000FFFFFFFFF000ULL; /* 48 bit PA */
 
        dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >=
                                        IP_VERSION(9, 4, 2) ?