static inline void set_badinstr_registers(CPUMIPSState *env)
{
+ CPUState *cs = env_cpu(env);
+ MemOpIdx oi;
+
if (env->insn_flags & ISA_NANOMIPS32) {
if (env->CP0_Config3 & (1 << CP0C3_BI)) {
- uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
+ uint32_t instr;
+
+ oi = make_memop_idx(mo_endian_env(env) | MO_UW, cpu_mmu_index(cs, true));
+ instr = cpu_ldw_code_mmu(env, env->active_tc.PC, oi, 0) << 16;
if ((instr & 0x10000000) == 0) {
- instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
+ instr |= cpu_ldw_code_mmu(env, env->active_tc.PC + 2, oi, 0);
}
env->CP0_BadInstr = instr;
if ((instr & 0xFC000000) == 0x60000000) {
- instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
+ instr = cpu_ldw_code_mmu(env, env->active_tc.PC + 4, oi, 0) << 16;
env->CP0_BadInstrX = instr;
}
}
/* TODO: add BadInstr support for microMIPS */
return;
}
+
+ oi = make_memop_idx(mo_endian_env(env) | MO_UL, cpu_mmu_index(cs, true));
if (env->CP0_Config3 & (1 << CP0C3_BI)) {
- env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
+ env->CP0_BadInstr = cpu_ldl_code_mmu(env, env->active_tc.PC, oi, 0);
}
if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
(env->hflags & MIPS_HFLAG_BMASK)) {
- env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
+ env->CP0_BadInstrP = cpu_ldl_code_mmu(env, env->active_tc.PC - 4, oi, 0);
}
}