intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val);
}
-void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void intel_alpm_lobf_disable(const struct intel_crtc_state *new_crtc_state)
{
- struct intel_display *display = to_intel_display(state);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- const struct intel_crtc_state *old_crtc_state =
- intel_atomic_get_old_crtc_state(state, crtc);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct intel_display *display = to_intel_display(new_crtc_state);
+ enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
struct intel_encoder *encoder;
- if (DISPLAY_VER(display) < 20)
- return;
-
- if (crtc_state->has_lobf || crtc_state->has_lobf == old_crtc_state->has_lobf)
- return;
-
for_each_intel_encoder_mask(display->drm, encoder,
- crtc_state->uapi.encoder_mask) {
+ new_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp;
if (!intel_encoder_is_dp(encoder))
if (!intel_dp_is_edp(intel_dp))
continue;
- if (old_crtc_state->has_lobf) {
- mutex_lock(&intel_dp->alpm.lock);
- intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0);
- drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n");
- mutex_unlock(&intel_dp->alpm.lock);
- }
+ mutex_lock(&intel_dp->alpm.lock);
+ intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0);
+ drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n");
+ mutex_unlock(&intel_dp->alpm.lock);
}
}
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
}
-void intel_alpm_post_plane_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void intel_alpm_lobf_enable(const struct intel_crtc_state *new_crtc_state)
{
- struct intel_display *display = to_intel_display(state);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- const struct intel_crtc_state *old_crtc_state =
- intel_atomic_get_old_crtc_state(state, crtc);
+ struct intel_display *display = to_intel_display(new_crtc_state);
struct intel_encoder *encoder;
- if (crtc_state->has_psr || !crtc_state->has_lobf ||
- crtc_state->has_lobf == old_crtc_state->has_lobf)
- return;
-
for_each_intel_encoder_mask(display->drm, encoder,
- crtc_state->uapi.encoder_mask) {
+ new_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp;
if (!intel_encoder_is_dp(encoder))
intel_dp = enc_to_intel_dp(encoder);
if (intel_dp_is_edp(intel_dp)) {
- intel_alpm_enable_sink(intel_dp, crtc_state);
- intel_alpm_configure(intel_dp, crtc_state);
+ intel_alpm_enable_sink(intel_dp, new_crtc_state);
+ intel_alpm_configure(intel_dp, new_crtc_state);
}
}
}
const struct intel_crtc_state *crtc_state);
void intel_alpm_enable_sink(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+void intel_alpm_lobf_disable(const struct intel_crtc_state *new_crtc_state);
void intel_alpm_port_configure(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-void intel_alpm_post_plane_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+void intel_alpm_lobf_enable(const struct intel_crtc_state *new_crtc_state);
void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
return is_disabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state);
}
+static bool intel_crtc_lobf_enabling(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ if (!new_crtc_state->hw.active)
+ return false;
+
+ return is_enabling(has_lobf, old_crtc_state, new_crtc_state);
+}
+
+static bool intel_crtc_lobf_disabling(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ if (!old_crtc_state->hw.active)
+ return false;
+
+ return is_disabling(has_lobf, old_crtc_state, new_crtc_state);
+}
+
#undef is_disabling
#undef is_enabling
adl_scaler_ecc_unmask(new_crtc_state);
}
- intel_alpm_post_plane_update(state, crtc);
+ if (intel_crtc_lobf_enabling(old_crtc_state, new_crtc_state))
+ intel_alpm_lobf_enable(new_crtc_state);
intel_psr_post_plane_update(state, crtc);
}
intel_atomic_get_new_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
- intel_alpm_pre_plane_update(state, crtc);
+ if (intel_crtc_lobf_disabling(old_crtc_state, new_crtc_state))
+ intel_alpm_lobf_disable(new_crtc_state);
+
intel_psr_pre_plane_update(state, crtc);
if (intel_crtc_vrr_disabling(state, crtc)) {