From 0850ae496d534847ec2c26744521c1bce04ec59d Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Mon, 13 Oct 2025 15:58:50 +0200
-Subject: [PATCH 2/3] net: airoha: npu: Add airoha_npu_soc_data struct
+Subject: [PATCH] net: airoha: npu: Add airoha_npu_soc_data struct
Introduce airoha_npu_soc_data structure in order to generalize per-SoC
NPU firmware info. Introduce airoha_npu_load_firmware utility routine.
drivers/net/ethernet/airoha/airoha_npu.c | 77 ++++++++++++++++--------
1 file changed, 51 insertions(+), 26 deletions(-)
+diff --git a/drivers/net/ethernet/airoha/airoha_npu.c b/drivers/net/ethernet/airoha/airoha_npu.c
+index 8c883f2b2d36b7..41944cc5f6b062 100644
--- a/drivers/net/ethernet/airoha/airoha_npu.c
+++ b/drivers/net/ethernet/airoha/airoha_npu.c
@@ -103,6 +103,16 @@ enum {
#define MBOX_MSG_FUNC_ID GENMASK(14, 11)
#define MBOX_MSG_STATIC_BUF BIT(5)
#define MBOX_MSG_STATUS GENMASK(4, 2)
-@@ -182,49 +192,53 @@ static int airoha_npu_send_msg(struct ai
+@@ -182,49 +192,53 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
return ret;
}
-static int airoha_npu_run_firmware(struct device *dev, void __iomem *base,
-- struct reserved_mem *rmem)
+- struct resource *res)
+static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr,
+ const struct airoha_npu_fw *fw_info)
{
goto out;
}
-- addr = devm_ioremap(dev, rmem->base, rmem->size);
+- addr = devm_ioremap_resource(dev, res);
- if (IS_ERR(addr)) {
- ret = PTR_ERR(addr);
- goto out;
- goto out;
- }
+static int airoha_npu_run_firmware(struct device *dev, void __iomem *base,
-+ struct reserved_mem *rmem)
++ struct resource *res)
+{
+ const struct airoha_npu_soc_data *soc;
+ void __iomem *addr;
+ return -EINVAL;
- return ret;
-+ addr = devm_ioremap(dev, rmem->base, rmem->size);
++ addr = devm_ioremap_resource(dev, res);
+ if (IS_ERR(addr))
+ return PTR_ERR(addr);
+
}
static irqreturn_t airoha_npu_mbox_handler(int irq, void *npu_instance)
-@@ -596,8 +610,19 @@ void airoha_npu_put(struct airoha_npu *n
+@@ -597,8 +611,19 @@ void airoha_npu_put(struct airoha_npu *npu)
}
EXPORT_SYMBOL_GPL(airoha_npu_put);
From 4043b0c45f8555a079bdac69a19ed08695a47a7b Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Fri, 7 Nov 2025 00:57:04 +0100
-Subject: [PATCH 1/5] pinctrl: airoha: generalize pins/group/function/confs
+Subject: [PATCH] pinctrl: airoha: generalize pins/group/function/confs
handling
In preparation for support of Airoha AN7583, generalize
drivers/pinctrl/mediatek/pinctrl-airoha.c | 567 ++++++++++++----------
1 file changed, 318 insertions(+), 249 deletions(-)
+diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+index f1cf2578fe423e..32e5c1b32d5071 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -30,15 +30,15 @@
PINCTRL_PIN(0, "uart1_txd"),
PINCTRL_PIN(1, "uart1_rxd"),
PINCTRL_PIN(2, "i2c_scl"),
-@@ -427,172 +457,172 @@ static struct pinctrl_pin_desc airoha_pi
+@@ -427,172 +457,172 @@ static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
PINCTRL_PIN(63, "pcie_reset2"),
};
};
static const char *const pon_groups[] = { "pon" };
-@@ -1955,33 +1985,33 @@ static const struct airoha_pinctrl_func_
+@@ -1955,33 +1985,33 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
},
};
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
-@@ -2042,7 +2072,7 @@ static const struct airoha_pinctrl_conf
+@@ -2042,7 +2072,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
};
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
-@@ -2103,7 +2133,7 @@ static const struct airoha_pinctrl_conf
+@@ -2103,7 +2133,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
};
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
-@@ -2164,7 +2194,7 @@ static const struct airoha_pinctrl_conf
+@@ -2164,7 +2194,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
};
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
-@@ -2225,7 +2255,7 @@ static const struct airoha_pinctrl_conf
+@@ -2225,7 +2255,7 @@ static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
};
PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
-@@ -2547,12 +2577,17 @@ airoha_pinctrl_get_conf_reg(const struct
+@@ -2546,12 +2576,17 @@ airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf,
}
static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
if (!reg)
return -EINVAL;
-@@ -2565,12 +2600,17 @@ static int airoha_pinctrl_get_conf(struc
+@@ -2564,12 +2599,17 @@ static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
}
static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
if (!reg)
return -EINVAL;
-@@ -2583,44 +2623,34 @@ static int airoha_pinctrl_set_conf(struc
+@@ -2582,44 +2622,34 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
}
#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
(pin), (val))
static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
-@@ -2799,12 +2829,13 @@ static int airoha_pinconf_set(struct pin
+@@ -2796,12 +2826,13 @@ static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev,
static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
unsigned int group, unsigned long *config)
{
config))
return -ENOTSUPP;
-@@ -2821,13 +2852,14 @@ static int airoha_pinconf_group_set(stru
+@@ -2818,13 +2849,14 @@ static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev,
unsigned int group, unsigned long *configs,
unsigned int num_configs)
{
configs, num_configs);
if (err)
return err;
-@@ -2853,23 +2885,16 @@ static const struct pinctrl_ops airoha_p
+@@ -2850,23 +2882,16 @@ static const struct pinctrl_ops airoha_pctlops = {
.dt_free_map = pinconf_generic_dt_free_map,
};
--static struct pinctrl_desc airoha_pinctrl_desc = {
+-static const struct pinctrl_desc airoha_pinctrl_desc = {
- .name = KBUILD_MODNAME,
- .owner = THIS_MODULE,
- .pctlops = &airoha_pctlops,
pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
if (!pinctrl)
return -ENOMEM;
-@@ -2884,14 +2909,23 @@ static int airoha_pinctrl_probe(struct p
+@@ -2881,14 +2906,23 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
pinctrl->chip_scu = map;
err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
grp->pins, grp->npins,
-@@ -2904,10 +2938,10 @@ static int airoha_pinctrl_probe(struct p
+@@ -2901,10 +2935,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
}
/* build functions */
- func = &airoha_pinctrl_funcs[i];
+ func = &data->funcs[i];
- err = pinmux_generic_add_function(pinctrl->ctrl,
- func->desc.name,
- func->desc.groups,
-@@ -2920,6 +2954,10 @@ static int airoha_pinctrl_probe(struct p
+ err = pinmux_generic_add_pinfunction(pinctrl->ctrl,
+ &func->desc,
+ (void *)func);
+@@ -2915,6 +2949,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
}
}
err = pinctrl_enable(pinctrl->ctrl);
if (err)
return err;
-@@ -2928,8 +2966,39 @@ static int airoha_pinctrl_probe(struct p
+@@ -2923,8 +2961,39 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
}
From 579839c9548cf2a85e873ad787bc2fa6610bf8ab Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Fri, 7 Nov 2025 00:57:05 +0100
-Subject: [PATCH 2/5] pinctrl: airoha: convert PHY LED GPIO to macro
+Subject: [PATCH] pinctrl: airoha: convert PHY LED GPIO to macro
PHY LED GPIO pinctrl struct definition is very similar across the
different 4 PHY and 2 LED and it can be generelized to a macro.
drivers/pinctrl/mediatek/pinctrl-airoha.c | 588 ++++------------------
1 file changed, 100 insertions(+), 488 deletions(-)
+diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+index 32e5c1b32d5071..cb0edc2a66a1e6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -1473,516 +1473,128 @@ static const struct airoha_pinctrl_func_
+@@ -1473,516 +1473,128 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
},
};
From 1552ad5d649cff9d170e5bc1d13ab1487333b4b7 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Fri, 7 Nov 2025 00:57:06 +0100
-Subject: [PATCH 3/5] pinctrl: airoha: convert PWM GPIO to macro
+Subject: [PATCH] pinctrl: airoha: convert PWM GPIO to macro
The PWM GPIO struct definition follow the same pattern for every GPIO
pin hence it can be converted to a macro.
drivers/pinctrl/mediatek/pinctrl-airoha.c | 465 ++++------------------
1 file changed, 68 insertions(+), 397 deletions(-)
+diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+index cb0edc2a66a1e6..f3cf48bdd1f83d 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -1073,404 +1073,75 @@ static const struct airoha_pinctrl_func_
+@@ -1073,404 +1073,75 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
};
/* PWM */
From 3ffeb17a9a27a668efb6fbd074835e187910a9bb Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Fri, 7 Nov 2025 00:57:08 +0100
-Subject: [PATCH 5/5] pinctrl: airoha: add support for Airoha AN7583 PINs
+Subject: [PATCH] pinctrl: airoha: add support for Airoha AN7583 PINs
Add all the required entry to add suppot for Airoha AN7583 PINs.
drivers/pinctrl/mediatek/pinctrl-airoha.c | 747 +++++++++++++++++++++-
1 file changed, 740 insertions(+), 7 deletions(-)
+diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+index f3cf48bdd1f83d..bfcedc7f920b1e 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -70,6 +70,7 @@
#define UART1_RXD_PD_MASK BIT(3)
#define UART1_TXD_PD_MASK BIT(2)
#define I2C_SCL_PD_MASK BIT(1)
-@@ -625,10 +642,223 @@ static const struct pingroup en7581_pinc
+@@ -625,10 +642,223 @@ static const struct pingroup en7581_pinctrl_groups[] = {
PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
};
static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
"hsuart_cts_rts", "uart4",
"uart5" };
-@@ -641,11 +871,16 @@ static const char *const pcm_spi_groups[
+@@ -641,11 +871,16 @@ static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
"pcm_spi_cs2_p156",
"pcm_spi_cs2_p128",
"pcm_spi_cs3", "pcm_spi_cs4" };
static const char *const pwm_groups[] = { "gpio0", "gpio1",
"gpio2", "gpio3",
"gpio4", "gpio5",
-@@ -684,6 +919,22 @@ static const char *const phy3_led1_group
+@@ -684,6 +919,22 @@ static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
"gpio45", "gpio46" };
static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
"gpio45", "gpio46" };
static const struct airoha_pinctrl_func_group pon_func_group[] = {
{
-@@ -761,6 +1012,25 @@ static const struct airoha_pinctrl_func_
+@@ -761,6 +1012,25 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = {
},
};
static const struct airoha_pinctrl_func_group uart_func_group[] = {
{
.name = "uart2",
-@@ -1002,6 +1272,73 @@ static const struct airoha_pinctrl_func_
+@@ -1002,6 +1272,73 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
},
};
static const struct airoha_pinctrl_func_group i2s_func_group[] = {
{
.name = "i2s",
-@@ -1072,6 +1409,28 @@ static const struct airoha_pinctrl_func_
+@@ -1072,6 +1409,28 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
},
};
/* PWM */
#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
{ \
-@@ -1268,6 +1627,94 @@ static const struct airoha_pinctrl_func_
+@@ -1268,6 +1627,94 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
-@@ -1294,6 +1741,31 @@ static const struct airoha_pinctrl_func
+@@ -1294,6 +1741,31 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
-@@ -1355,6 +1827,62 @@ static const struct airoha_pinctrl_conf
+@@ -1355,6 +1827,62 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
-@@ -1416,6 +1944,62 @@ static const struct airoha_pinctrl_conf
+@@ -1416,6 +1944,62 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
-@@ -1477,6 +2061,62 @@ static const struct airoha_pinctrl_conf
+@@ -1477,6 +2061,62 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
-@@ -1538,12 +2178,73 @@ static const struct airoha_pinctrl_conf
+@@ -1538,12 +2178,73 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
};
static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
struct pinctrl_gpio_range *range,
int pin)
-@@ -1709,7 +2410,7 @@ static const struct irq_chip airoha_gpio
+@@ -1708,7 +2409,7 @@ static const struct irq_chip airoha_gpio_irq_chip = {
};
static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
{
struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
struct gpio_chip *gc = &chip->chip;
-@@ -1744,7 +2445,7 @@ static int airoha_pinctrl_add_gpiochip(s
+@@ -1743,7 +2444,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
return irq;
err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
if (err) {
dev_err(dev, "error requesting irq %d: %d\n", irq, err);
return err;
-@@ -1808,8 +2509,8 @@ static int airoha_pinmux_set_mux(struct
+@@ -1807,8 +2508,8 @@ static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
}
static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev,
{
struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
u32 mask, index;
-@@ -1899,7 +2600,7 @@ static int airoha_pinctrl_set_conf(struc
+@@ -1898,7 +2599,7 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,
return -EINVAL;
return 0;
-@@ -2118,8 +2819,8 @@ static int airoha_pinconf_group_get(stru
+@@ -2115,8 +2816,8 @@ static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
for (i = 0; i < pinctrl->grps[group].npins; i++) {
if (airoha_pinconf_get(pctrl_dev,
return -ENOTSUPP;
if (i && cur_config != *config)
-@@ -2280,8 +2981,40 @@ static const struct airoha_pinctrl_match
+@@ -2275,8 +2976,40 @@ static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
},
};
# M: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
-@@ -72,16 +72,7 @@ config PHY_CAN_TRANSCEIVER
+@@ -102,16 +102,6 @@ config PHY_CAN_TRANSCEIVER
functional modes using gpios and sets the attribute max link
rate, for CAN drivers.
- This driver create the basic PHY instance and provides initialize
- callback for PCIe GEN3 port.
-
+ config PHY_NXP_PTN3222
+ tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"
+ depends on I2C
+@@ -123,6 +113,7 @@ config PHY_NXP_PTN3222
+ schemes. It supports all three USB 2.0 data rates: Low Speed, Full
+ Speed and High Speed.
+
+source "drivers/phy/airoha/Kconfig"
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
-@@ -10,8 +10,8 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy
- obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
+@@ -13,9 +13,9 @@ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
+ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
-obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
--obj-y += allwinner/ \
-+obj-y += airoha/ \
+ obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
+-obj-$(CONFIG_GENERIC_PHY) += allwinner/ \
++obj-$(CONFIG_GENERIC_PHY) += airoha/ \
+ allwinner/ \
amlogic/ \
broadcom/ \
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
-@@ -51,4 +51,6 @@ config PCS_RZN1_MIIC
- on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
- pass-through mode for MII.
+@@ -55,4 +55,6 @@ config PCS_RZN1_MIIC
+ Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to
+ RMII/RGMII, or can be set in pass-through mode for MII.
+source "drivers/net/pcs/airoha/Kconfig"
+
endmenu
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
-@@ -10,3 +10,5 @@ obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
+@@ -10,3 +10,4 @@ obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
- obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
obj-$(CONFIG_PCS_MTK_USXGMII) += pcs-mtk-usxgmii.o
-+
+ obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
+obj-$(CONFIG_PCS_AIROHA) += airoha/
--- /dev/null
+++ b/drivers/net/pcs/airoha/Kconfig
+endif
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c
-@@ -0,0 +1,1312 @@
+@@ -0,0 +1,1313 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+}
+
+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
-+ int index, struct phylink_link_state *state)
++ int index, unsigned int neg_mode,
++ struct phylink_link_state *state)
+{
+ struct airoha_pcs_maps *maps = &priv->maps[index];
+ u32 bmsr, lpa;
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+ lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
+
-+ phylink_mii_c22_pcs_decode_state(state, bmsr, lpa);
++ phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
+}
+
+static void airoha_pcs_get_state_hsgmii(struct airoha_pcs_priv *priv, int index,
+}
+
+static void airoha_pcs_get_state(struct phylink_pcs *pcs,
++ unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_port *port = to_airoha_pcs_port(pcs);
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
-+ airoha_pcs_get_state_sgmii(priv, port->index, state);
++ airoha_pcs_get_state_sgmii(priv, port->index, neg_mode, state);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_get_state_hsgmii(priv, port->index, state);
+ port->priv = priv;
+ port->index = index;
+ port->pcs.poll = true;
-+ port->pcs.neg_mode = true;
+ port->pcs.ops = &airoha_pcs_ops;
+
+ switch (data->port_type) {
unsigned int quot);
int fsl8250_handle_irq(struct uart_port *port);
+int en7523_set_uart_baud_rate(struct uart_port *port, unsigned int baud);
+ void serial8250_handle_irq_locked(struct uart_port *port, unsigned int iir);
int serial8250_handle_irq(struct uart_port *port, unsigned int iir);
u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr);
- void serial8250_read_char(struct uart_8250_port *up, u16 lsr);
struct dst_entry *dst_cache;
--- a/net/netfilter/nf_flow_table_ip.c
+++ b/net/netfilter/nf_flow_table_ip.c
-@@ -372,6 +372,7 @@ static int nf_flow_offload_forward(struc
+@@ -376,6 +376,7 @@ static int nf_flow_offload_forward(struc
struct flow_offload *flow;
unsigned int thoff, mtu;
struct iphdr *iph;
dir = tuplehash->tuple.dir;
flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);
-@@ -401,6 +402,12 @@ static int nf_flow_offload_forward(struc
+@@ -405,6 +406,12 @@ static int nf_flow_offload_forward(struc
iph = ip_hdr(skb);
nf_flow_nat_ip(flow, skb, thoff, dir, iph);
ip_decrease_ttl(iph);
skb_clear_tstamp(skb);
-@@ -651,6 +658,7 @@ static int nf_flow_offload_ipv6_forward(
+@@ -655,6 +662,7 @@ static int nf_flow_offload_ipv6_forward(
struct flow_offload *flow;
unsigned int thoff, mtu;
struct ipv6hdr *ip6h;
dir = tuplehash->tuple.dir;
flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);
-@@ -679,6 +687,12 @@ static int nf_flow_offload_ipv6_forward(
+@@ -683,6 +691,12 @@ static int nf_flow_offload_ipv6_forward(
ip6h = ipv6_hdr(skb);
nf_flow_nat_ipv6(flow, skb, dir, ip6h);
#include <linux/netfilter/nf_conntrack_common.h>
#include <linux/netfilter/nf_tables.h>
+#include <net/dsfield.h>
- #include <net/ip.h> /* for ipv4 options. */
- #include <net/inet_dscp.h>
+ #include <net/ip.h>
+ #include <net/flow.h>
#include <net/netfilter/nf_tables.h>
@@ -279,6 +280,27 @@ static int nft_flow_route(const struct n
return 0;
u8 fport);
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
-@@ -297,12 +297,12 @@ static void airoha_ppe_foe_set_bridge_ad
+@@ -299,12 +299,12 @@ static void airoha_ppe_foe_set_bridge_ad
static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
struct airoha_foe_entry *hwe,
struct airoha_foe_mac_info_common *l2;
u8 smac_id = 0xf;
-@@ -318,10 +318,11 @@ static int airoha_ppe_foe_entry_prepare(
+@@ -320,10 +320,11 @@ static int airoha_ppe_foe_entry_prepare(
hwe->ib1 = val;
val = FIELD_PREP(AIROHA_FOE_IB2_PORT_AG, 0x1f);
val |= FIELD_PREP(AIROHA_FOE_IB2_NBQ, info.idx) |
FIELD_PREP(AIROHA_FOE_IB2_PSE_PORT,
FE_PSE_PORT_CDM4);
-@@ -331,12 +332,14 @@ static int airoha_ppe_foe_entry_prepare(
+@@ -333,12 +334,14 @@ static int airoha_ppe_foe_entry_prepare(
FIELD_PREP(AIROHA_FOE_MAC_WDMA_WCID,
info.wcid);
} else {
if (dsa_port >= 0 || eth->ports[1])
pse_port = port->id == 4 ? FE_PSE_PORT_GDM4
: port->id;
-@@ -1483,7 +1486,7 @@ void airoha_ppe_check_skb(struct airoha_
+@@ -1485,7 +1488,7 @@ void airoha_ppe_check_skb(struct airoha_
void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port)
{
struct airoha_eth *eth = port->qdma->eth;
airoha_ppe_set_cpu_port(dev, i, AIROHA_GDM2_IDX);
if (port->id == AIROHA_GDM4_IDX && airoha_is_7581(eth)) {
-- u32 mask = FC_ID_OF_SRC_PORT_MASK(port->nbq);
+- u32 mask = FC_ID_OF_SRC_PORT_MASK(nbq);
+ u32 mask = FC_ID_OF_SRC_PORT_MASK(dev->nbq);
airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, mask,
projects / thirdparty / openwrt.git / commitdiff
