--- /dev/null
+From fee4380f368e84ed216b62ccd2fbc4126f2bf40b Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@free-electrons.com>
+Date: Mon, 18 Dec 2017 11:32:45 +0100
+Subject: mtd: nand: pxa3xx: Fix READOOB implementation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Boris Brezillon <boris.brezillon@free-electrons.com>
+
+commit fee4380f368e84ed216b62ccd2fbc4126f2bf40b upstream.
+
+In the current driver, OOB bytes are accessed in raw mode, and when a
+page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the
+driver must read the whole spare area (64 bytes in case of a 2k page,
+16 bytes for a 512 page). The driver was only reading the free OOB
+bytes, which was leaving some unread data in the FIFO and was somehow
+leading to a timeout.
+
+We could patch the driver to read ->spare_size + ->ecc_size instead of
+just ->spare_size when READOOB is requested, but we'd better make
+in-band and OOB accesses consistent.
+Since the driver is always accessing in-band data in non-raw mode (with
+the ECC engine enabled), we should also access OOB data in this mode.
+That's particularly useful when using the BCH engine because in this
+mode the free OOB bytes are also ECC protected.
+
+Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support")
+Reported-by: Sean Nyekjær <sean.nyekjaer@prevas.dk>
+Tested-by: Willy Tarreau <w@1wt.eu>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
+Tested-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
+Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mtd/nand/pxa3xx_nand.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mtd/nand/pxa3xx_nand.c
++++ b/drivers/mtd/nand/pxa3xx_nand.c
+@@ -950,6 +950,7 @@ static void prepare_start_command(struct
+
+ switch (command) {
+ case NAND_CMD_READ0:
++ case NAND_CMD_READOOB:
+ case NAND_CMD_PAGEPROG:
+ info->use_ecc = 1;
+ break;
--- /dev/null
+From 88776c0e70be0290f8357019d844aae15edaa967 Mon Sep 17 00:00:00 2001
+From: Helge Deller <deller@gmx.de>
+Date: Tue, 2 Jan 2018 20:36:44 +0100
+Subject: parisc: Fix alignment of pa_tlb_lock in assembly on 32-bit SMP kernel
+
+From: Helge Deller <deller@gmx.de>
+
+commit 88776c0e70be0290f8357019d844aae15edaa967 upstream.
+
+Qemu for PARISC reported on a 32bit SMP parisc kernel strange failures
+about "Not-handled unaligned insn 0x0e8011d6 and 0x0c2011c9."
+
+Those opcodes evaluate to the ldcw() assembly instruction which requires
+(on 32bit) an alignment of 16 bytes to ensure atomicity.
+
+As it turns out, qemu is correct and in our assembly code in entry.S and
+pacache.S we don't pay attention to the required alignment.
+
+This patch fixes the problem by aligning the lock offset in assembly
+code in the same manner as we do in our C-code.
+
+Signed-off-by: Helge Deller <deller@gmx.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/parisc/include/asm/ldcw.h | 2 ++
+ arch/parisc/kernel/entry.S | 13 +++++++++++--
+ arch/parisc/kernel/pacache.S | 9 +++++++--
+ 3 files changed, 20 insertions(+), 4 deletions(-)
+
+--- a/arch/parisc/include/asm/ldcw.h
++++ b/arch/parisc/include/asm/ldcw.h
+@@ -11,6 +11,7 @@
+ for the semaphore. */
+
+ #define __PA_LDCW_ALIGNMENT 16
++#define __PA_LDCW_ALIGN_ORDER 4
+ #define __ldcw_align(a) ({ \
+ unsigned long __ret = (unsigned long) &(a)->lock[0]; \
+ __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
+@@ -28,6 +29,7 @@
+ ldcd). */
+
+ #define __PA_LDCW_ALIGNMENT 4
++#define __PA_LDCW_ALIGN_ORDER 2
+ #define __ldcw_align(a) (&(a)->slock)
+ #define __LDCW "ldcw,co"
+
+--- a/arch/parisc/kernel/entry.S
++++ b/arch/parisc/kernel/entry.S
+@@ -35,6 +35,7 @@
+ #include <asm/pgtable.h>
+ #include <asm/signal.h>
+ #include <asm/unistd.h>
++#include <asm/ldcw.h>
+ #include <asm/thread_info.h>
+
+ #include <linux/linkage.h>
+@@ -46,6 +47,14 @@
+ #endif
+
+ .import pa_tlb_lock,data
++ .macro load_pa_tlb_lock reg
++#if __PA_LDCW_ALIGNMENT > 4
++ load32 PA(pa_tlb_lock) + __PA_LDCW_ALIGNMENT-1, \reg
++ depi 0,31,__PA_LDCW_ALIGN_ORDER, \reg
++#else
++ load32 PA(pa_tlb_lock), \reg
++#endif
++ .endm
+
+ /* space_to_prot macro creates a prot id from a space id */
+
+@@ -457,7 +466,7 @@
+ .macro tlb_lock spc,ptp,pte,tmp,tmp1,fault
+ #ifdef CONFIG_SMP
+ cmpib,COND(=),n 0,\spc,2f
+- load32 PA(pa_tlb_lock),\tmp
++ load_pa_tlb_lock \tmp
+ 1: LDCW 0(\tmp),\tmp1
+ cmpib,COND(=) 0,\tmp1,1b
+ nop
+@@ -480,7 +489,7 @@
+ /* Release pa_tlb_lock lock. */
+ .macro tlb_unlock1 spc,tmp
+ #ifdef CONFIG_SMP
+- load32 PA(pa_tlb_lock),\tmp
++ load_pa_tlb_lock \tmp
+ tlb_unlock0 \spc,\tmp
+ #endif
+ .endm
+--- a/arch/parisc/kernel/pacache.S
++++ b/arch/parisc/kernel/pacache.S
+@@ -36,6 +36,7 @@
+ #include <asm/assembly.h>
+ #include <asm/pgtable.h>
+ #include <asm/cache.h>
++#include <asm/ldcw.h>
+ #include <linux/linkage.h>
+
+ .text
+@@ -333,8 +334,12 @@ ENDPROC_CFI(flush_data_cache_local)
+
+ .macro tlb_lock la,flags,tmp
+ #ifdef CONFIG_SMP
+- ldil L%pa_tlb_lock,%r1
+- ldo R%pa_tlb_lock(%r1),\la
++#if __PA_LDCW_ALIGNMENT > 4
++ load32 pa_tlb_lock + __PA_LDCW_ALIGNMENT-1, \la
++ depi 0,31,__PA_LDCW_ALIGN_ORDER, \la
++#else
++ load32 pa_tlb_lock, \la
++#endif
+ rsm PSW_SM_I,\flags
+ 1: LDCW 0(\la),\tmp
+ cmpib,<>,n 0,\tmp,3f
--- /dev/null
+From 310d82784fb4d60c80569f5ca9f53a7f3bf1d477 Mon Sep 17 00:00:00 2001
+From: Helge Deller <deller@gmx.de>
+Date: Fri, 5 Jan 2018 21:55:38 +0100
+Subject: parisc: qemu idle sleep support
+
+From: Helge Deller <deller@gmx.de>
+
+commit 310d82784fb4d60c80569f5ca9f53a7f3bf1d477 upstream.
+
+Add qemu idle sleep support when running under qemu with SeaBIOS PDC
+firmware.
+
+Like the power architecture we use the "or" assembler instructions,
+which translate to nops on real hardware, to indicate that qemu shall
+idle sleep.
+
+Signed-off-by: Helge Deller <deller@gmx.de>
+Cc: Richard Henderson <rth@twiddle.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/parisc/kernel/process.c | 39 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+--- a/arch/parisc/kernel/process.c
++++ b/arch/parisc/kernel/process.c
+@@ -39,6 +39,7 @@
+ #include <linux/kernel.h>
+ #include <linux/mm.h>
+ #include <linux/fs.h>
++#include <linux/cpu.h>
+ #include <linux/module.h>
+ #include <linux/personality.h>
+ #include <linux/ptrace.h>
+@@ -181,6 +182,44 @@ int dump_task_fpu (struct task_struct *t
+ }
+
+ /*
++ * Idle thread support
++ *
++ * Detect when running on QEMU with SeaBIOS PDC Firmware and let
++ * QEMU idle the host too.
++ */
++
++int running_on_qemu __read_mostly;
++
++void __cpuidle arch_cpu_idle_dead(void)
++{
++ /* nop on real hardware, qemu will offline CPU. */
++ asm volatile("or %%r31,%%r31,%%r31\n":::);
++}
++
++void __cpuidle arch_cpu_idle(void)
++{
++ local_irq_enable();
++
++ /* nop on real hardware, qemu will idle sleep. */
++ asm volatile("or %%r10,%%r10,%%r10\n":::);
++}
++
++static int __init parisc_idle_init(void)
++{
++ const char *marker;
++
++ /* check QEMU/SeaBIOS marker in PAGE0 */
++ marker = (char *) &PAGE0->pad0;
++ running_on_qemu = (memcmp(marker, "SeaBIOS", 8) == 0);
++
++ if (!running_on_qemu)
++ cpu_idle_poll_ctrl(1);
++
++ return 0;
++}
++arch_initcall(parisc_idle_init);
++
++/*
+ * Copy architecture-specific thread state
+ */
+ int
arc-uaccess-dont-use-l-gcc-inline-asm-constraint-modifier.patch
input-elantech-add-new-icbody-type-15.patch
x86-microcode-amd-add-support-for-fam17h-microcode-loading.patch
+parisc-fix-alignment-of-pa_tlb_lock-in-assembly-on-32-bit-smp-kernel.patch
+parisc-qemu-idle-sleep-support.patch
+mtd-nand-pxa3xx-fix-readoob-implementation.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
