}
}
+static void ath9k_hw_clear_rxdesc_status(struct ar5416_desc *ads)
+{
+ WRITE_ONCE(ads->u.rx.status0, 0);
+ WRITE_ONCE(ads->u.rx.status1, 0);
+ WRITE_ONCE(ads->u.rx.status2, 0);
+ WRITE_ONCE(ads->u.rx.status3, 0);
+ WRITE_ONCE(ads->u.rx.status4, 0);
+ WRITE_ONCE(ads->u.rx.status5, 0);
+ WRITE_ONCE(ads->u.rx.status6, 0);
+ WRITE_ONCE(ads->u.rx.status7, 0);
+ WRITE_ONCE(ads->u.rx.status8, 0);
+}
+
void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
u32 size, u32 flags)
{
if (flags & ATH9K_RXDESC_INTREQ)
ads->ds_ctl1 |= AR_RxIntrReq;
- memset(&ads->u.rx, 0, sizeof(ads->u.rx));
+ ath9k_hw_clear_rxdesc_status(ads);
}
EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
return true;
}
+static void ath9k_hw_clear_txstatus(struct ar9003_txs *ads)
+{
+ WRITE_ONCE(ads->ds_info, 0);
+ WRITE_ONCE(ads->status1, 0);
+ WRITE_ONCE(ads->status2, 0);
+ WRITE_ONCE(ads->status3, 0);
+ WRITE_ONCE(ads->status4, 0);
+ WRITE_ONCE(ads->status5, 0);
+ WRITE_ONCE(ads->status6, 0);
+ WRITE_ONCE(ads->status7, 0);
+ WRITE_ONCE(ads->status8, 0);
+}
+
static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
struct ath_tx_status *ts)
{
(MS(ads->ds_info, AR_TxRxDesc) != 1)) {
ath_dbg(ath9k_hw_common(ah), XMIT,
"Tx Descriptor error %x\n", ads->ds_info);
- memset(ads, 0, sizeof(*ads));
+ ath9k_hw_clear_txstatus(ads);
return -EIO;
}
ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
- memset(ads, 0, sizeof(*ads));
+ ath9k_hw_clear_txstatus(ads);
return 0;
}
void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
{
+ int i;
+
ah->ts_tail = 0;
- memset((void *) ah->ts_ring, 0,
- ah->ts_size * sizeof(struct ar9003_txs));
+ for (i = 0; i < ah->ts_size; i++)
+ ath9k_hw_clear_txstatus(&ah->ts_ring[i]);
ath_dbg(ath9k_hw_common(ah), XMIT,
"TS Start 0x%x End 0x%x Virt %p, Size %d\n",