mediatek: filogic: kn-1812: fix phy reset deassert

The RTL8261BE 10GbE PHY's `reset-deassert-us` was set to 100ms (100000us),
but the **RTL8261N datasheet (Table 108, parameter t7)** specifies a
minimum **SMI-ready time of 150ms** after nRESET release before the MDIO
(SMI) bus can be used.

Note: Essentially, the RTL8261N and RTL8261BE are architecturally identical
chips, so their initialization parameters should be consistent.

Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22575
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

diff --git a/target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi b/target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi
index 1eb534dbc452c728221f16018fb0bf84bfa59e69..140ae1528b6bcccc9c65c8bbab099b2cc3ee073d 100644 (file)
--- a/target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi
+++ b/target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi
@@ -400,7 +400,7 @@
 
                reset-gpios = <&pio 4 GPIO_ACTIVE_LOW>;
                reset-assert-us = <100000>;
-               reset-deassert-us = <100000>;
+               reset-deassert-us = <221000>;
        };
 };