clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
base + 0x10, 0x3));
+ clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc",
+ base + 0xa0, 0x7f));
+ clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6",
+ "osc", base + 0xe0, 0x3));
+
clk_dm(IMX6QDL_CLK_PLL3_60M,
imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8));
clk_dm(IMX6QDL_CLK_PLL3_80M,
imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6));
clk_dm(IMX6QDL_CLK_PLL3_120M,
imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4));
- clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc",
- base + 0xa0, 0x7f));
clk_dm(IMX6QDL_CLK_PLL5_VIDEO,
imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13));
- clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6",
- "osc", base + 0xe0, 0x3));
clk_dm(IMX6QDL_CLK_PLL6_ENET,
imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13));
ldb_di_sels, ARRAY_SIZE(ldb_di_sels)));
} else {
/*
- * Need to set these as read-only due to a hardware bug.
- * Keeping default mux values. Fixed on the i.MX6 QuadPlus
- */
+ * Need to set these as read-only due to a hardware bug.
+ * Keeping default mux values. Fixed on the i.MX6 QuadPlus
+ */
clk_dm(IMX6QDL_CLK_LDB_DI0_SEL,
imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3,
ldb_di_sels, ARRAY_SIZE(ldb_di_sels),