]> git.ipfire.org Git - thirdparty/valgrind.git/commitdiff
s390x: Fix vec3 test case when using clang
authorAndreas Arnez <arnez@linux.ibm.com>
Fri, 20 Mar 2026 12:11:03 +0000 (13:11 +0100)
committerAndreas Arnez <arnez@linux.ibm.com>
Fri, 20 Mar 2026 12:58:10 +0000 (13:58 +0100)
The llvm assembler behaves differently from gas when dealing with
unassigned bits in an .insn directive.  While gas fills them with the
given instruction text, clang sets them to zeroes.

In the VRR format this affects bits 20-23:

+--------+----+----+----+---+----+----+----+------------+
| OpCode | V1 | V2 | V3 |///| M6 | M5 | M4 |   Opcode   |
+--------+----+----+----+---+----+----+----+------------+
0        8    12   16       24   28   32   36           47

The `vec3' test case exploits filling these bits in TEST_V3OP, thus it
fails when compiled with clang.  Fix this by using VRI instead of VRR and
assigning fixed registers to the missing vector operands in that format.

The issue also applies to TEST_VBLEND, but since VBLEND is just another
3-input-operand instruction, treat it like that and drop the special
handling.

none/tests/s390x/vec3.c
none/tests/s390x/vec3.stdout.exp

index d8d569ff1a81193387e2d1be0d8731ea4a653133..6438d8b122f686977a6734f07c77dc86d8eabb8a 100644 (file)
@@ -39,29 +39,6 @@ static void test_all_veval(void)
    TEST_VEVAL(f, f);
 }
 
-/* -- Vector blend -- */
-
-#define TEST_VBLEND(m5)                                                        \
-   {                                                                           \
-      ulong_v          out;                                                    \
-      register ulong_v c __asm__("v4") = vc;                                   \
-      __asm__(".insn vrr,0xe7000" #m5 "000089,%0,%1,%2,4,0,0"                  \
-              : [out] "=v"(out)                                                \
-              : "v"(va), "v"(vb), "v"(c)                                       \
-              :);                                                              \
-      printf("\t%016lx %016lx\n", out[0], out[1]);                             \
-   }
-
-static void test_all_vblend(void)
-{
-   puts("vblend");
-   TEST_VBLEND(0);
-   TEST_VBLEND(1);
-   TEST_VBLEND(2);
-   TEST_VBLEND(3);
-   TEST_VBLEND(4);
-}
-
 /* -- Vector generate element masks -- */
 
 #define TEST_VGEM(m3, op)                                                      \
@@ -293,17 +270,25 @@ static void test_all_v2op(void)
 #define TEST_V3OP(m5, opc, a, b, c)                                            \
    {                                                                           \
       ulong_v          out;                                                    \
+      register ulong_v v3 __asm__("v3") = b;                                   \
       register ulong_v v4 __asm__("v4") = c;                                   \
                                                                                \
-      __asm__(".insn vrr,0xe7000" #m5 "0000" opc ",%0,%1,%2,4,0,0"             \
+      __asm__(".insn vri,0xe700000000" opc ",%0,%1,0x3" #m5 "0,4,0"            \
               : [out] "=v"(out)                                                \
-              : "v"(a), "v"(b), "v"(v4)                                        \
+              : "v"(a), "v"(v3), "v"(v4)                                       \
               :);                                                              \
       printf("\t%016lx %016lx\n", out[0], out[1]);                             \
    }
 
 static void test_all_v3op(void)
 {
+   puts("vblend");
+   TEST_V3OP(0, "89", va, vb, vc);
+   TEST_V3OP(1, "89", va, vb, vc);
+   TEST_V3OP(2, "89", va, vb, vc);
+   TEST_V3OP(3, "89", va, vb, vc);
+   TEST_V3OP(4, "89", va, vb, vc);
+
    puts("vmae");
    TEST_V3OP(3, "ae", v8, vc, v0);
    TEST_V3OP(3, "ae", va, vb, vc);
@@ -395,7 +380,6 @@ static void test_all_vec(void)
 int main(void)
 {
    test_all_veval();
-   test_all_vblend();
    test_all_vgem();
    test_all_v1op();
    test_all_v2op();
index a1ebce65f8add62c2c7401ac0468cd5996057781..1992d41ee789ece6f06f785c051cdcf60f527b76 100644 (file)
@@ -6,12 +6,6 @@ veval
        0000444444440440 0000010101808080
        5666aaaaaaaa6a26 bcfe4e74ba722e5c
        ffffffffffffffff ffffffffffffffff
-vblend
-       bbaabbbbbbbbaaaa 6789ccf0aa0f5533
-       bbbbbbbbbbbbaaaa 6789ccf0aa335533
-       bbbbbbbbbbbbbbbb 6789f0aaaa330f55
-       bbbbbbbbbbbbbbbb 6789f0aa4c0f5533
-       bbbbbbbbbbbbbbbb 6789f0aa4c0f5533
 vgem
        00ff00ff00ffff00 ff00ff00ff00ff00
        0000ffff0000ffff 0000ffffffff0000
@@ -153,6 +147,12 @@ vmlh
        3f8e38e38e38e38e 29bc214695ac6999
        004510000000412f 6b8dab5e0679dbaa
        ffffffffffffffff fffffffffffffffe
+vblend
+       bbaabbbbbbbbaaaa 6789ccf0aa0f5533
+       bbbbbbbbbbbbaaaa 6789ccf0aa335533
+       bbbbbbbbbbbbbbbb 6789f0aaaa330f55
+       bbbbbbbbbbbbbbbb 6789f0aa4c0f5533
+       bbbbbbbbbbbbbbbb 6789f0aa4c0f5533
 vmae
        ff99ffffffff9fba 0000000000000000
        e9af8e38e38ef96f 8e622da51dd80b3d