dt-bindings: clock: qcom: document the Glymur GPU Clock Controller

Glymur SoC has Qualcomm GX(graphics) clock controller and also the
Graphics clock controller. The GX graphics clock controller helps in the
recovery of the Graphics subsystem.

Add bindings documentation for the Glymur Graphics Clock and Graphics
power domain Controller for Glymur SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260127-glymur_gpucc-v1-1-547334c81ba2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
index 5490a975f3db7d253a17cc13a67f6c44e0d47ef3..55bf3f8110171e9d14a2d0f7ba8e0089a31177cc 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
@@ -20,6 +20,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,glymur-gxclkctl
       - qcom,kaanapali-gxclkctl
 
   power-domains:

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
index 6feaa32569f9a852c2049fee00ee7a2e2aefb558..5993804c91fa564b29f8dd0650c9efad498f543d 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
@@ -13,7 +13,8 @@ description: |
   Qualcomm graphics clock control module provides the clocks, resets and power
   domains on Qualcomm SoCs.
 
-  See also::
+  See also:
+    include/dt-bindings/clock/qcom,glymur-gpucc.h
     include/dt-bindings/clock/qcom,kaanapali-gpucc.h
     include/dt-bindings/clock/qcom,milos-gpucc.h
     include/dt-bindings/clock/qcom,sar2130p-gpucc.h
@@ -27,6 +28,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,glymur-gpucc
       - qcom,kaanapali-gpucc
       - qcom,milos-gpucc
       - qcom,sar2130p-gpucc

diff --git a/include/dt-bindings/clock/qcom,glymur-gpucc.h b/include/dt-bindings/clock/qcom,glymur-gpucc.h
new file mode 100644 (file)
index 0000000..35f5abb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-gpucc.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK                                         0
+#define GPU_CC_CB_CLK                                          1
+#define GPU_CC_CX_ACCU_SHIFT_CLK                               2
+#define GPU_CC_CX_FF_CLK                                       3
+#define GPU_CC_CX_GMU_CLK                                      4
+#define GPU_CC_CXO_AON_CLK                                     5
+#define GPU_CC_CXO_CLK                                         6
+#define GPU_CC_DEMET_CLK                                       7
+#define GPU_CC_DPM_CLK                                         8
+#define GPU_CC_FF_CLK_SRC                                      9
+#define GPU_CC_FREQ_MEASURE_CLK                                        10
+#define GPU_CC_GMU_CLK_SRC                                     11
+#define GPU_CC_GPU_SMMU_VOTE_CLK                               12
+#define GPU_CC_GX_ACCU_SHIFT_CLK                               13
+#define GPU_CC_GX_ACD_AHB_FF_CLK                               14
+#define GPU_CC_GX_AHB_FF_CLK                                   15
+#define GPU_CC_GX_GMU_CLK                                      16
+#define GPU_CC_GX_RCG_AHB_FF_CLK                               17
+#define GPU_CC_HUB_AON_CLK                                     18
+#define GPU_CC_HUB_CLK_SRC                                     19
+#define GPU_CC_HUB_CX_INT_CLK                                  20
+#define GPU_CC_HUB_DIV_CLK_SRC                                 21
+#define GPU_CC_MEMNOC_GFX_CLK                                  22
+#define GPU_CC_PLL0                                            23
+#define GPU_CC_PLL0_OUT_EVEN                                   24
+#define GPU_CC_RSCC_HUB_AON_CLK                                        25
+#define GPU_CC_RSCC_XO_AON_CLK                                 26
+#define GPU_CC_SLEEP_CLK                                       27
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC                                         0
+
+/* GPU_CC resets */
+#define GPU_CC_CB_BCR                                          0
+#define GPU_CC_CX_BCR                                          1
+#define GPU_CC_FAST_HUB_BCR                                    2
+#define GPU_CC_FF_BCR                                          3
+#define GPU_CC_GMU_BCR                                         4
+#define GPU_CC_GX_BCR                                          5
+#define GPU_CC_XO_BCR                                          6
+
+#endif