]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm64: dts: amlogic: meson-s4: add internal SARADC controller
authorNick Xie <nick@khadas.com>
Wed, 25 Mar 2026 07:06:17 +0000 (15:06 +0800)
committerNeil Armstrong <neil.armstrong@linaro.org>
Tue, 2 Jun 2026 07:49:45 +0000 (09:49 +0200)
Add the SARADC (Successive Approximation Register ADC) controller
node to the Meson S4 SoC dtsi.

It uses the S4-specific compatible string with a fallback to the
G12A generation, as there are no known hardware differences.

Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Nick Xie <nick@khadas.com>
Link: https://patch.msgid.link/20260325070618.81955-4-nick@khadas.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
arch/arm64/boot/dts/amlogic/meson-s4.dtsi

index 4a3e9ad82d2809379b9ed7feb546d69d3904b37a..936a5c1353d15986f65ea9c1d63743e119408bf6 100644 (file)
                };
        };
 
+       saradc: adc@fe026000 {
+               compatible = "amlogic,meson-s4-saradc",
+                            "amlogic,meson-g12a-saradc";
+               reg = <0x0 0xfe026000 0x0 0x48>;
+               #io-channel-cells = <1>;
+               interrupts = <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>;
+               clocks = <&xtal>,
+                        <&clkc_periphs CLKID_SAR_ADC>,
+                        <&clkc_periphs CLKID_SARADC>,
+                        <&clkc_periphs CLKID_SARADC_SEL>;
+               clock-names = "clkin", "core", "adc_clk", "adc_sel";
+               status = "disabled";
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <2>;