drm/amdgpu: Align amdgpu_gtt_mgr entries to TLB size on Tahiti (v2)

The TLB is organized in groups of 8 entries, each one is 4K.
On Tahiti, the HW requires these GART entries to be 32K-aligned.

This fixes a VCE 1 firmware validation failure that can happen
after suspend/resume since we use amdgpu_gtt_mgr for VCE 1.

v2:
- Change variable declaration order
- Add comment about "V bit HW bug"

Fixes: 698fa62f56aa ("drm/amdgpu: Add helper to alloc GART entries")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 530411b465ef0b2c0cc18c2e3d7e38422b1117d1)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 620fddde4c4dd0647d34622c1fd766332e16debb..a5d26b943f6d48f5065eaf4f134b92518f9cf278 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -199,11 +199,18 @@ int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr,
                                 enum drm_mm_insert_mode mode)
 {
        struct amdgpu_device *adev = container_of(mgr, typeof(*adev), mman.gtt_mgr);
+       u32 alignment = 0;
        int r;
 
+       /* Align to TLB L2 cache entry size to work around "V bit HW bug" */
+       if (adev->asic_type == CHIP_TAHITI) {
+               alignment = 32 * 1024 / AMDGPU_GPU_PAGE_SIZE;
+               num_pages = ALIGN(num_pages, alignment);
+       }
+
        spin_lock(&mgr->lock);
        r = drm_mm_insert_node_in_range(&mgr->mm, mm_node, num_pages,
-                                       0, GART_ENTRY_WITHOUT_BO_COLOR, 0,
+                                       alignment, GART_ENTRY_WITHOUT_BO_COLOR, 0,
                                        adev->gmc.gart_size >> PAGE_SHIFT,
                                        mode);
        spin_unlock(&mgr->lock);