spi: microchip-core-qspi: fix setting spi bus clock rate

commit ef13561d2b163ac0ae6befa53bca58a26dc3320b upstream.

Before ORing the new clock rate with the control register value read
from the hardware, the existing clock rate needs to be masked off as
otherwise the existing value will interfere with the new one.

CC: stable@vger.kernel.org
Fixes: 8596124c4c1b ("spi: microchip-core-qspi: Add support for microchip fpga qspi controllers")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240508-fox-unpiloted-b97e1535627b@spud
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microchip-core-qspi.c
index 19a6a46829f6d963ee671701e9b5a299fc6cdc6e..620c5d19031e2d1c16543803c63bd3ec03a79ee7 100644 (file)
--- a/drivers/spi/spi-microchip-core-qspi.c
+++ b/drivers/spi/spi-microchip-core-qspi.c
@@ -283,6 +283,7 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_devi
        }
 
        control = readl_relaxed(qspi->regs + REG_CONTROL);
+       control &= ~CONTROL_CLKRATE_MASK;
        control |= baud_rate_val << CONTROL_CLKRATE_SHIFT;
        writel_relaxed(control, qspi->regs + REG_CONTROL);
        control = readl_relaxed(qspi->regs + REG_CONTROL);