#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <asm/msr.h>
-#include <asm/processor.h>
+#include <linux/processor.h>
#include <asm/cpu_device_id.h>
#include <linux/sched/isolation.h>
* which are covered by tjmax_table
*/
{ INTEL_ATOM_BONNELL_MID, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx)
- * Note: TjMax for E6xxT is 110C, but CPU type
- * is undetectable by software
+ * Note: TjMax for E6xxT is 110C, but CPU
+ * type is undetectable by software
*/
{ INTEL_ATOM_SALTWELL_MID, ANY, 90000 }, /* Atom Medfield (Z2460) */
{ INTEL_ATOM_SALTWELL_TABLET, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */
{ INTEL_ATOM_SALTWELL, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx)
- * Also matches S12x0 (stepping 9), covered by
- * PCI table
+ * Also matches S12x0 (stepping 9), covered
+ * by PCI table
*/
{ INTEL_ATOM_SILVERMONT, 9, 110000 }, /* Atom Bay Trail E38xx (embedded) */
{ INTEL_ATOM_SILVERMONT, ANY, 90000 }, /* Atom Bay Trail Z37xx (tablet) */
for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
const struct tjmax_model *tm = &tjmax_model_table[i];
+
if (c->x86_vfm == tm->vfm &&
(tm->stepping_mask == ANY ||
tm->stepping_mask == c->x86_stepping))
err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
if (err) {
dev_warn(dev,
- "Unable to access MSR 0x17, assuming desktop"
- " CPU\n");
+ "Unable to access MSR 0x17, assuming desktop CPU\n");
usemsr_ee = 0;
} else if (c->x86_vfm < INTEL_CORE2_PENRYN &&
!(eax & 0x10000000)) {
err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
if (err) {
dev_warn(dev,
- "Unable to access MSR 0xEE, for Tjmax, left"
- " at default\n");
+ "Unable to access MSR 0xEE, for Tjmax, left at default\n");
} else if (eax & 0x40000000) {
tjmax = tjmax_ee;
}
static struct platform_device **zone_devices;
static ssize_t show_label(struct device *dev,
- struct device_attribute *devattr, char *buf)
+ struct device_attribute *devattr, char *buf)
{
struct platform_data *pdata = dev_get_drvdata(dev);
struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_LABEL]);
}
static ssize_t show_crit_alarm(struct device *dev,
- struct device_attribute *devattr, char *buf)
+ struct device_attribute *devattr, char *buf)
{
u32 eax, edx;
struct temp_data *tdata = container_of(devattr, struct temp_data,
}
static ssize_t show_tjmax(struct device *dev,
- struct device_attribute *devattr, char *buf)
+ struct device_attribute *devattr, char *buf)
{
struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TJMAX]);
int tjmax;
}
static ssize_t show_ttarget(struct device *dev,
- struct device_attribute *devattr, char *buf)
+ struct device_attribute *devattr, char *buf)
{
struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TTARGET]);
int ttarget;
}
static ssize_t show_temp(struct device *dev,
- struct device_attribute *devattr, char *buf)
+ struct device_attribute *devattr, char *buf)
{
u32 eax, edx;
struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TEMP]);
static int create_core_attrs(struct temp_data *tdata, struct device *dev)
{
- int i;
static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev,
struct device_attribute *devattr, char *buf) = {
show_label, show_crit_alarm, show_temp, show_tjmax,
static const char *const suffixes[TOTAL_ATTRS] = {
"label", "crit_alarm", "input", "crit", "max"
};
+ int i;
for (i = 0; i < tdata->attr_size; i++) {
/*
return sysfs_create_group(&dev->kobj, &tdata->attr_group);
}
-
static int chk_ucode_version(unsigned int cpu)
{
struct cpuinfo_x86 *c = &cpu_data(cpu);
}
return 0;
}
-static const struct x86_cpu_id __initconst coretemp_ids[] = {
+
+static const struct x86_cpu_id coretemp_ids[] __initconst = {
X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_DTHERM, NULL),
{}
};