mtd: rawnand: ndfc: use ioread32be/iowrite32be and allow COMPILE_TEST

Replace ppc4xx-specific in_be32/out_be32 with generic ioread32be/
iowrite32be to make the driver portable. Add COMPILE_TEST dependency
to get build coverage on non-ppc4xx architectures.

While at it, replace 4xx with 44x. The latter was removed a while ago
and is only kept for compatibility.

Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 7408f34f0c68acaafaa09528483422914275d449..ee01b845694de0554815410243e0359de9b81590 100644 (file)
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -71,7 +71,7 @@ config MTD_NAND_AU1550
 
 config MTD_NAND_NDFC
        tristate "IBM/MCC 4xx NAND controller"
-       depends on 4xx
+       depends on 44x || COMPILE_TEST
        select MTD_NAND_ECC_SW_HAMMING
        select MTD_NAND_ECC_SW_HAMMING_SMC
        help

diff --git a/drivers/mtd/nand/raw/ndfc.c b/drivers/mtd/nand/raw/ndfc.c
index 7ad8bc04be1a5bffd8040b51b86cb2014eb6d602..a937ca3eeff5657656dfd4b4e55d2606bc3f0ae2 100644 (file)
--- a/drivers/mtd/nand/raw/ndfc.c
+++ b/drivers/mtd/nand/raw/ndfc.c
@@ -44,13 +44,13 @@ static void ndfc_select_chip(struct nand_chip *nchip, int chip)
        uint32_t ccr;
        struct ndfc_controller *ndfc = nand_get_controller_data(nchip);
 
-       ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
+       ccr = ioread32be(ndfc->ndfcbase + NDFC_CCR);
        if (chip >= 0) {
                ccr &= ~NDFC_CCR_BS_MASK;
                ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
        } else
                ccr |= NDFC_CCR_RESET_CE;
-       out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
+       iowrite32be(ccr, ndfc->ndfcbase + NDFC_CCR);
 }
 
 static void ndfc_hwcontrol(struct nand_chip *chip, int cmd, unsigned int ctrl)
@@ -70,7 +70,7 @@ static int ndfc_ready(struct nand_chip *chip)
 {
        struct ndfc_controller *ndfc = nand_get_controller_data(chip);
 
-       return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
+       return ioread32be(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
 }
 
 static void ndfc_enable_hwecc(struct nand_chip *chip, int mode)
@@ -78,9 +78,9 @@ static void ndfc_enable_hwecc(struct nand_chip *chip, int mode)
        uint32_t ccr;
        struct ndfc_controller *ndfc = nand_get_controller_data(chip);
 
-       ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
+       ccr = ioread32be(ndfc->ndfcbase + NDFC_CCR);
        ccr |= NDFC_CCR_RESET_ECC;
-       out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
+       iowrite32be(ccr, ndfc->ndfcbase + NDFC_CCR);
        wmb();
 }
 
@@ -92,7 +92,7 @@ static int ndfc_calculate_ecc(struct nand_chip *chip,
        uint8_t *p = (uint8_t *)&ecc;
 
        wmb();
-       ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
+       ecc = ioread32be(ndfc->ndfcbase + NDFC_ECC);
        /* The NDFC uses Smart Media (SMC) bytes order */
        ecc_code[0] = p[1];
        ecc_code[1] = p[2];
@@ -114,7 +114,7 @@ static void ndfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
        uint32_t *p = (uint32_t *) buf;
 
        for(;len > 0; len -= 4)
-               *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
+               *p++ = ioread32be(ndfc->ndfcbase + NDFC_DATA);
 }
 
 static void ndfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
@@ -123,7 +123,7 @@ static void ndfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
        uint32_t *p = (uint32_t *) buf;
 
        for(;len > 0; len -= 4)
-               out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
+               iowrite32be(*p++, ndfc->ndfcbase + NDFC_DATA);
 }
 
 /*
@@ -223,13 +223,13 @@ static int ndfc_probe(struct platform_device *ofdev)
        if (reg)
                ccr |= be32_to_cpup(reg);
 
-       out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
+       iowrite32be(ccr, ndfc->ndfcbase + NDFC_CCR);
 
        /* Set the bank settings if given */
        reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
        if (reg) {
                int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
-               out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
+               iowrite32be(be32_to_cpup(reg), ndfc->ndfcbase + offset);
        }
 
        err = ndfc_chip_init(ndfc, ofdev->dev.of_node);