ramips: mt76x8: adapt to upstream PWM driver

Fix register offsets and clock sources for MT7628 hardware variant.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22214
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

diff --git a/target/linux/ramips/patches-6.12/102-01-pwm-mediatek-set-mt7628-pwm45_fixup-flag-to-false.patch b/target/linux/ramips/patches-6.12/102-01-pwm-mediatek-set-mt7628-pwm45_fixup-flag-to-false.patch
new file mode 100644 (file)
index 0000000..130b877
--- /dev/null
+++ b/target/linux/ramips/patches-6.12/102-01-pwm-mediatek-set-mt7628-pwm45_fixup-flag-to-false.patch
@@ -0,0 +1,25 @@
+From 2ff84ce933de37e91d132553a2555c4b4e9dedc8 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Tue, 24 Feb 2026 15:32:42 +0800
+Subject: [PATCH 1/2] pwm: mediatek: set mt7628 pwm45_fixup flag to false
+
+According to the programing guide, mt7628 has generic register layout
+like most other hardware revisions. We should not set pwm45_fixup flag
+for it.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pwm/pwm-mediatek.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -324,7 +324,7 @@ static const struct pwm_mediatek_of_data
+ 
+ static const struct pwm_mediatek_of_data mt7628_pwm_data = {
+       .num_pwms = 4,
+-      .pwm45_fixup = true,
++      .pwm45_fixup = false,
+       .has_ck_26m_sel = false,
+       .reg_offset = mtk_pwm_reg_offset_v1,
+ };

diff --git a/target/linux/ramips/patches-6.12/102-02-pwm-mediatek-correct-mt7628-clock-source-setting.patch b/target/linux/ramips/patches-6.12/102-02-pwm-mediatek-correct-mt7628-clock-source-setting.patch
new file mode 100644 (file)
index 0000000..498eb7f
--- /dev/null
+++ b/target/linux/ramips/patches-6.12/102-02-pwm-mediatek-correct-mt7628-clock-source-setting.patch
@@ -0,0 +1,65 @@
+From 1d846d6f80f24066747dac57440c84502a8a1cd3 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Tue, 24 Feb 2026 16:19:54 +0800
+Subject: [PATCH 2/2] pwm: mediatek: correct mt7628 clock source setting
+
+PWMCON register Bit(3) is used to configure whether to pre divide
+the clock source. Most revisions clear this bit to disable frequency
+division. However, mt7628 needs to set this bit. Hence, we introduce
+a new clksel_fixup flag to correctly configure the clock source for
+mt7628.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pwm/pwm-mediatek.c | 23 ++++++++++++++++++++++-
+ 1 file changed, 22 insertions(+), 1 deletion(-)
+
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -21,6 +21,8 @@
+ 
+ /* PWM registers and bits definitions */
+ #define PWMCON                        0x00
++#define PWMCON_CLKSEL                 BIT(3)
++#define PWMCON_OLD_PWM_MODE           BIT(15)
+ #define PWMHDUR                       0x04
+ #define PWMLDUR                       0x08
+ #define PWMGDUR                       0x0c
+@@ -35,6 +37,7 @@
+ 
+ struct pwm_mediatek_of_data {
+       unsigned int num_pwms;
++      bool clksel_fixup;
+       bool pwm45_fixup;
+       bool has_ck_26m_sel;
+       const unsigned int *reg_offset;
+@@ -141,6 +144,7 @@ static int pwm_mediatek_config(struct pw
+       struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
+       u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
+           reg_thres = PWMTHRES;
++      u32 con_val;
+       unsigned long clk_rate;
+       u64 resolution;
+       int ret;
+@@ -191,7 +195,12 @@ static int pwm_mediatek_config(struct pw
+ 
+       cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
+ 
+-      pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
++      con_val = PWMCON_OLD_PWM_MODE | clkdiv;
++      /* Set BIT(3) to disable clock division */
++      if (pc->soc->clksel_fixup)
++              con_val |= PWMCON_CLKSEL;
++
++      pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, con_val);
+       pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period - 1);
+ 
+       if (cnt_duty) {
+@@ -324,6 +333,7 @@ static const struct pwm_mediatek_of_data
+ 
+ static const struct pwm_mediatek_of_data mt7628_pwm_data = {
+       .num_pwms = 4,
++      .clksel_fixup = true,
+       .pwm45_fixup = false,
+       .has_ck_26m_sel = false,
+       .reg_offset = mtk_pwm_reg_offset_v1,