drm/i915/cx0: Drop C20 25.175 MHz rate

Drop C20 25.175 MHz PLL table as with these
PLL dividers the port clock will be incorrectly
calculated to 25.2 MHz. For 25.175 MHz rate the
PLl dividers are calculated algorithmically making
PLL table for this rate redundant.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-14-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ce4b7582b73777364c3578d74f9d76eb0d63b4c6..a0af7d3e87b6ed33a20f5c14dd77fe1db1a3480d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1798,31 +1798,6 @@ static const struct intel_cx0pll_params mtl_c10_hdmi_tables[] = {
        {}
 };
 
-static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
-       .clock = 25175,
-       .tx = {  0xbe88, /* tx cfg0 */
-                 0x9800, /* tx cfg1 */
-                 0x0000, /* tx cfg2 */
-               },
-       .cmn = { 0x0500, /* cmn cfg0*/
-                 0x0005, /* cmn cfg1 */
-                 0x0000, /* cmn cfg2 */
-                 0x0000, /* cmn cfg3 */
-               },
-       .mpllb = { 0xa0d2,      /* mpllb cfg0 */
-                  0x7d80,      /* mpllb cfg1 */
-                  0x0906,      /* mpllb cfg2 */
-                  0xbe40,      /* mpllb cfg3 */
-                  0x0000,      /* mpllb cfg4 */
-                  0x0000,      /* mpllb cfg5 */
-                  0x0200,      /* mpllb cfg6 */
-                  0x0001,      /* mpllb cfg7 */
-                  0x0000,      /* mpllb cfg8 */
-                  0x0000,      /* mpllb cfg9 */
-                  0x0001,      /* mpllb cfg10 */
-               },
-};
-
 static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
        .clock = 27000,
        .tx = {  0xbe88, /* tx cfg0 */
@@ -2049,7 +2024,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
 };
 
 static const struct intel_cx0pll_params mtl_c20_hdmi_tables[] = {
-       C20PLL_HDMI_PARAMS(25175, mtl_c20_hdmi_25_175),
        C20PLL_HDMI_PARAMS(27000, mtl_c20_hdmi_27_0),
        C20PLL_HDMI_PARAMS(74250, mtl_c20_hdmi_74_25),
        C20PLL_HDMI_PARAMS(148500, mtl_c20_hdmi_148_5),