drm/i915/display: Add upper limit check for pixel clock

Add upper limit check for pixel clock for DISPLAY_VER >= 30.
Limits don't apply when DSC is enabled.

The helper returns the upper limit for the platforms, capped to the
max dotclock (khz).

For the currently supported versions of HDMI, pixel clock is already
limited to 600Mhz so nothing needs to be done there as of now.

v2:
 - Add this limit to the new helper.
v3:
 - Rename helper to intel_max_uncompressed_dotclock(). (Imre)
 - Limit only for PTL and cap the limit to max_dotclock. (Imre)

BSpec: 49199, 68912
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260202103731.357416-17-ankit.k.nautiyal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d107b686378118c7ea1d867c6a9fc579048cae9a..4f5f64e22cb5d0d9eadd5eddd404363e8ff61526 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8026,6 +8026,17 @@ void intel_setup_outputs(struct intel_display *display)
        drm_helper_move_panel_connectors_to_head(display->drm);
 }
 
+int intel_max_uncompressed_dotclock(struct intel_display *display)
+{
+       int max_dotclock = display->cdclk.max_dotclk_freq;
+       int limit = max_dotclock;
+
+       if (DISPLAY_VER(display) >= 30)
+               limit = 1350000;
+
+       return min(max_dotclock, limit);
+}
+
 static int max_dotclock(struct intel_display *display)
 {
        int max_dotclock = display->cdclk.max_dotclk_freq;

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 4cced16af8cef5c5e16e2677dce46f3564c3dac7..552a59d19e0f621081c88d0ea2f6bd0cf7ff7159 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -462,6 +462,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
                                    struct intel_link_m_n *m_n);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
+int intel_max_uncompressed_dotclock(struct intel_display *display);
 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
 enum intel_display_power_domain
 intel_aux_power_domain(struct intel_digital_port *dig_port);

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 60a789d93222d3099fa3d95488aa83cee1114797..e2fd01d1a1e488071555d4436895cf01348ae5c2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1428,6 +1428,9 @@ bool intel_dp_dotclk_valid(struct intel_display *display,
                                                                         target_clock,
                                                                         htotal,
                                                                         dsc_slice_count);
+       else
+               effective_dotclk_limit =
+                       intel_max_uncompressed_dotclock(display) * num_joined_pipes;
 
        return target_clock <= effective_dotclk_limit;
 }