[RISC-V] Fix expected testsuite output after ext-dce changes

The recent changes to ext-dce can transform sign extension to zero extension in
some cases.  As a result tests which previously expected a signed load can now
see an unsigned load.  Of course on rv32 "lw" loads a full word, so this
doesn't show up there.  So instead of looking for "lw" we instead look for
"(lwu|lw)".  This fixes the "regressions" after the ext-dce changes.

gcc/testsuite
	* gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: Adjust expected
	output.
	* gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: Likewise.
	* gcc.target/riscv/amo/a-rvwmo-store-release.c: Likewise.
	* gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: Likewise.
	* gcc.target/riscv/amo/a-ztso-store-relaxed.c: Likewise.
	* gcc.target/riscv/amo/a-ztso-store-release.c: Likewise.
	* gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c: Likewise.
	* gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c: Likewise.
	* gcc.target/riscv/amo/zalasr-rvwmo-store-release.c: Likewise.
	* gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c: Likewise.
	* gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c: Likewise.
	* gcc.target/riscv/amo/zalasr-ztso-store-release.c: Likewise.
	* gcc.target/riscv/cpymem-64-ooo.c: Likewise.
	* gcc.target/riscv/cpymem-64.c: Likewise.
	* gcc.target/riscv/memcpy-nonoverlapping.c: Likewise.
	* gcc.target/riscv/pr67731.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
index b3ec4e1061b1904f58ef8a706335b21790608ebb..25d1110829a62d9d8aa5f1932788a7690977398d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
@@ -22,7 +22,7 @@ void atomic_store_long_seq_cst (long* bar, long* baz)
 
 /*
 ** atomic_store_int_seq_cst:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     fence\trw,w
 **     sw\t[atx][0-9]+,0\(a0\)
 **     fence\trw,rw

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
index 2f224f993de44a206946b48cfe81f16de91df661..87b0f2fead58cdd5913d2ad427fb78aa9c296f52 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
@@ -19,7 +19,7 @@ void atomic_store_long_relaxed (long* bar, long* baz)
 
 /*
 ** atomic_store_int_relaxed:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
index 6daca225d2407660c9487e365419922089a81cb3..9e75c8d3b4d7b99095c124d1455f6c9e65cff9e1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
@@ -20,7 +20,7 @@ void atomic_store_long_release (long* bar, long* baz)
 
 /*
 ** atomic_store_int_release:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     fence\trw,w
 **     sw\t[atx][0-9]+,0\(a0\)
 **     ret

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
index a1cefbb11097cb26ce24ba01f42cedf517d437c2..ff96ab7fa18b9299afb796f55a3a3727346fab45 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
@@ -21,7 +21,7 @@ void atomic_store_long_seq_cst (long* bar, long* baz)
 
 /*
 ** atomic_store_int_seq_cst:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw\t[atx][0-9]+,0\(a0\)
 **     fence\trw,rw
 **     ret

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
index 939ad757462569a023a1dce9c8708c6d9f6891ea..41e081b768bae953b4dd29ec1dab538f43254861 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
@@ -19,7 +19,7 @@ void atomic_store_long_relaxed (long* bar, long* baz)
 
 /*
 ** atomic_store_int_relaxed:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
index bb97b8a6d5243f8363a45300a1082124c65a378a..f55e4a12795711b47e813c5b4f71f7a482d58c4e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
@@ -19,7 +19,7 @@ void atomic_store_long_release (long* bar, long* baz)
 
 /*
 ** atomic_store_int_release:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
index 7f40d443bd0cde7acbd32e1eb759fc09e4ff5356..03324eed14fe8f1177e29a543948f2508c4bc139 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
@@ -20,7 +20,7 @@ void atomic_store_long_seq_cst (long* bar, long* baz)
 
 /*
 ** atomic_store_int_seq_cst:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw.rl\t[atx][0-9]+,0\(a0\)
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
index d0127e53baa273216629279690459ce299948378..daefe4582ed0f88daba26510d27d9bcafefd7891 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
@@ -19,7 +19,7 @@ void atomic_store_long_relaxed (long* bar, long* baz)
 
 /*
 ** atomic_store_int_relaxed:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
index 6174718fe2dd72ecf4a0f54f8a8fd77c72843e68..2b26a24f950bb435a02d977d2f24b484909e9a04 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
@@ -19,7 +19,7 @@ void atomic_store_long_release (long* bar, long* baz)
 
 /*
 ** atomic_store_int_release:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw.rl\t[atx][0-9]+,0\(a0\)
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
index 085f94e5d42f864b1e2e0daa4793c1623aabfb6d..c53c0f0a424d020d9760d94f5c1f136aa70945d6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
@@ -20,7 +20,7 @@ void atomic_store_long_seq_cst (long* bar, long* baz)
 
 /*
 ** atomic_store_int_seq_cst:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw.rl\t[atx][0-9]+,0\(a0\)
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
index cb68849291b0df8bc71ac360a9f176e9c92169fe..c637da07810aefb877b64d432521489935d033a8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
@@ -19,7 +19,7 @@ void atomic_store_long_relaxed (long* bar, long* baz)
 
 /*
 ** atomic_store_int_relaxed:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
index b5cc2e967d2a4cdfeeca7d7e911e2537f123c945..01c86adf4bd61a8cc95198b07bda96f34828a2c4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
@@ -19,7 +19,7 @@ void atomic_store_long_release (long* bar, long* baz)
 
 /*
 ** atomic_store_int_release:
-**     lw\t[atx][0-9]+,0\(a1\)
+**     (lwu|lw)\t[atx][0-9]+,0\(a1\)
 **     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/cpymem-64-ooo.c b/gcc/testsuite/gcc.target/riscv/cpymem-64-ooo.c
index 147324093cb15171c22e023f98ac29e0c5538038..77d38d5e573307e4b181906618e8c6a3fbb513f5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/cpymem-64-ooo.c
+++ b/gcc/testsuite/gcc.target/riscv/cpymem-64-ooo.c
@@ -22,9 +22,9 @@ void copy_aligned_##N (void *to, void *from)          \
 /*
 **copy_7:
 **    ...
-**    lw\t[at][0-9],0\([at][0-9]\)
+**    (lwu|lw)\t[at][0-9],0\([at][0-9]\)
 **    sw\t[at][0-9],0\([at][0-9]\)
-**    lw\t[at][0-9],3\([at][0-9]\)
+**    (lwu|lw)\t[at][0-9],3\([at][0-9]\)
 **    sw\t[at][0-9],3\([at][0-9]\)
 **    ...
 */
@@ -33,9 +33,9 @@ COPY_N(7)
 /*
 **copy_aligned_7:
 **    ...
-**    lw\t[at][0-9],0\([at][0-9]\)
+**    (lwu|lw)\t[at][0-9],0\([at][0-9]\)
 **    sw\t[at][0-9],0\([at][0-9]\)
-**    lw\t[at][0-9],3\([at][0-9]\)
+**    (lwu|lw)\t[at][0-9],3\([at][0-9]\)
 **    sw\t[at][0-9],3\([at][0-9]\)
 **    ...
 */
@@ -64,7 +64,7 @@ COPY_ALIGNED_N(8)
 **    ...
 **    ld\t[at][0-9],0\([at][0-9]\)
 **    sd\t[at][0-9],0\([at][0-9]\)
-**    lw\t[at][0-9],7\([at][0-9]\)
+**    (lwu|lw)\t[at][0-9],7\([at][0-9]\)
 **    sw\t[at][0-9],7\([at][0-9]\)
 **    ...
 */
@@ -75,7 +75,7 @@ COPY_N(11)
 **    ...
 **    ld\t[at][0-9],0\([at][0-9]\)
 **    sd\t[at][0-9],0\([at][0-9]\)
-**    lw\t[at][0-9],7\([at][0-9]\)
+**    (lwu|lw)\t[at][0-9],7\([at][0-9]\)
 **    sw\t[at][0-9],7\([at][0-9]\)
 **    ...
 */
@@ -110,7 +110,7 @@ COPY_ALIGNED_N(15)
 **    ...
 **    sd\t[at][0-9],16\([at][0-9]\)
 **    ...
-**    lw\t[at][0-9],23\([at][0-9]\)
+**    (lwu|lw)\t[at][0-9],23\([at][0-9]\)
 **    sw\t[at][0-9],23\([at][0-9]\)
 **    ...
 */
@@ -123,7 +123,7 @@ COPY_N(27)
 **    ...
 **    sd\t[at][0-9],16\([at][0-9]\)
 **    ...
-**    lw\t[at][0-9],23\([at][0-9]\)
+**    (lwu|lw)\t[at][0-9],23\([at][0-9]\)
 **    sw\t[at][0-9],23\([at][0-9]\)
 **    ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/cpymem-64.c b/gcc/testsuite/gcc.target/riscv/cpymem-64.c
index c91b0154a298e66cc725db84553a51ac70d48340..df3a679f15926227ecb8eeb91a2ea75b4d24f1e4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/cpymem-64.c
+++ b/gcc/testsuite/gcc.target/riscv/cpymem-64.c
@@ -35,7 +35,7 @@ COPY_N(7)
 /*
 **copy_aligned_7:
 **    ...
-**    lw\t[at][0-9],0\([at][0-9]\)
+**    (lwu|lw)\t[at][0-9],0\([at][0-9]\)
 **    sw\t[at][0-9],0\([at][0-9]\)
 **    ...
 **    lbu\t[at][0-9],6\([at][0-9]\)

diff --git a/gcc/testsuite/gcc.target/riscv/memcpy-nonoverlapping.c b/gcc/testsuite/gcc.target/riscv/memcpy-nonoverlapping.c
index 1c99e13fc269de7b7c1a6a6cce05a9b987a90a51..62f1497adf8395db7f8df306b2aed0f4cbf1706a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/memcpy-nonoverlapping.c
+++ b/gcc/testsuite/gcc.target/riscv/memcpy-nonoverlapping.c
@@ -44,7 +44,7 @@ COPY_N(31)
 /* { dg-final { scan-assembler-times "ld\t" 17 } } */
 /* { dg-final { scan-assembler-times "sd\t" 17 } } */
 
-/* { dg-final { scan-assembler-times "lw\t" 6 } } */
+/* { dg-final { scan-assembler-times "(lwu|lw)\t" 6 } } */
 /* { dg-final { scan-assembler-times "sw\t" 6 } } */
 
 /* { dg-final { scan-assembler-times "lhu\t" 7 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/pr67731.c b/gcc/testsuite/gcc.target/riscv/pr67731.c
index 6f254fc68f5f3668c4e9d40a78091af61e0587f9..4e6f609e24df6cedc6cd1f7846a7c36ee0209595 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/pr67731.c
+++ b/gcc/testsuite/gcc.target/riscv/pr67731.c
@@ -20,6 +20,7 @@ _Bool test_01 (S* s)
 {
   return s->b | s->c | s->d;
 }
-/* { dg-final { scan-assembler-times {\tlw\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 } } */
+/* { dg-final { scan-assembler-times {\tlw\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 { target rv32 } } } */
+/* { dg-final { scan-assembler-times {\tlwu\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 { target rv64 } } } */
 /* { dg-final { scan-assembler-not {\tor} } } */
 /* { dg-final { scan-assembler-not {\tbexti} } } */