]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915: Remove i915_reg.h from intel_rom.c
authorUma Shankar <uma.shankar@intel.com>
Thu, 5 Feb 2026 09:43:35 +0000 (15:13 +0530)
committerUma Shankar <uma.shankar@intel.com>
Thu, 12 Feb 2026 10:42:55 +0000 (16:12 +0530)
Make intel_rom.c free from including i915_reg.h.

v5: Use SPDX (Jani)

v4: Move oprom reg to separate header (Ville)

v3: Update patch header

v2: Use display header instead of gmd common include (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-15-uma.shankar@intel.com
drivers/gpu/drm/i915/display/intel_oprom_regs.h [new file with mode: 0644]
drivers/gpu/drm/i915/display/intel_rom.c
drivers/gpu/drm/i915/i915_reg.h

diff --git a/drivers/gpu/drm/i915/display/intel_oprom_regs.h b/drivers/gpu/drm/i915/display/intel_oprom_regs.h
new file mode 100644 (file)
index 0000000..e6a6fb5
--- /dev/null
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_OPROM_REGS_H_
+#define _INTEL_OPROM_REGS_H_
+
+#define PRIMARY_SPI_TRIGGER                    _MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS                    _MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID                   _MMIO(0x102084)
+#define SPI_STATIC_REGIONS                     _MMIO(0x102090)
+#define   OPTIONROM_SPI_REGIONID_MASK          REG_GENMASK(7, 0)
+#define OROM_OFFSET                            _MMIO(0x1020c0)
+#define   OROM_OFFSET_MASK                     REG_GENMASK(20, 16)
+
+#endif
index c8f615315310321c8f41cccacf7efed160cfd04f..024db7b1a1c6f2c19a266b755f4d3227f4a9aa51 100644 (file)
@@ -7,10 +7,9 @@
 
 #include <drm/drm_device.h>
 
-#include "i915_reg.h"
-
 #include "intel_rom.h"
 #include "intel_uncore.h"
+#include "intel_oprom_regs.h"
 
 struct intel_rom {
        /* for PCI ROM */
index 2c279bd3342dcf75b4340a1cbd9e301ebde7e0a4..9cb753b65bc245c1f714ba8b9b12096c50b1d914 100644 (file)
 #define   SGGI_DIS                     REG_BIT(15)
 #define   SGR_DIS                      REG_BIT(13)
 
-#define PRIMARY_SPI_TRIGGER                    _MMIO(0x102040)
-#define PRIMARY_SPI_ADDRESS                    _MMIO(0x102080)
-#define PRIMARY_SPI_REGIONID                   _MMIO(0x102084)
-#define SPI_STATIC_REGIONS                     _MMIO(0x102090)
-#define   OPTIONROM_SPI_REGIONID_MASK          REG_GENMASK(7, 0)
-#define OROM_OFFSET                            _MMIO(0x1020c0)
-#define   OROM_OFFSET_MASK                     REG_GENMASK(20, 16)
-
 #define MTL_MEDIA_GSI_BASE             0x380000
 
 #endif /* _I915_REG_H_ */