board: toradex: aquila-am69: Fix memory size setup logic

The hardware configuration pins are used both to select the DDR
configuration and to determine the installed memory size.

On Aquila AM69, the DDR timing patch is applied in the R5 SPL, while the
memory size fixup for the next-stage U-Boot DT is done later in the A72
SPL path.
The previous immplementation was not taking in account that the hw_cfg
value is lost both during SPL execution (board_init_f and board_init_r)
and between SPL and U-Boot proper.

Fix this by reading the hardware configuration pins when the memory size
is actually needed:
- in the R5 SPL, to select the correct DDR configuration
- in the A72 SPL, to fix up the U-Boot DT memory size and bank layout

Fixes: 3f0528882c0d ("board: toradex: add aquila am69 support")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>

diff --git a/board/toradex/aquila-am69/aquila-am69.c b/board/toradex/aquila-am69/aquila-am69.c
index 0c7123a059e4d5df2bc9681aa5cf6823e376edd5..45fba1bbfe806da6b54eac36cef91c8ad7985eb4 100644 (file)
--- a/board/toradex/aquila-am69/aquila-am69.c
+++ b/board/toradex/aquila-am69/aquila-am69.c
@@ -15,6 +15,7 @@
 #include <i2c.h>
 #include <linux/sizes.h>
 #include <spl.h>
+#include <asm/arch/k3-ddr.h>
 
 #include "../common/tdx-common.h"
 #include "aquila_ddrs.h"
@@ -30,46 +31,24 @@
 #define HW_CFG_MEM_CFG_MASK            0x03
 
 DECLARE_GLOBAL_DATA_PTR;
-static u8 hw_cfg;
 
-static u8 aquila_am69_memory_cfg(void)
-{
-       return hw_cfg & HW_CFG_MEM_CFG_MASK;
-}
-
-static u64 aquila_am69_memory_size(void)
-{
-       switch (aquila_am69_memory_cfg()) {
-       case HW_CFG_MEM_SZ_32GB:
-               return SZ_32G;
-       case HW_CFG_MEM_SZ_16GB_RANK_2:
-       case HW_CFG_MEM_SZ_16GB:
-               return SZ_16G;
-       case HW_CFG_MEM_SZ_8GB:
-               return SZ_8G;
-       default:
-               puts("Invalid memory size configuration\n");
-               return -EINVAL;
-       }
-}
-
-static void read_hw_cfg(void)
+static u8 get_hw_cfg(void)
 {
        struct gpio_desc gpio_hw_cfg;
        char gpio_name[20];
+       u8 hw_cfg = 0;
        int i;
 
-       printf("HW CFG: ");
        for (i = 0; i < 5; i++) {
                sprintf(gpio_name, "gpio@42110000_%d", 82 + i);
                if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) {
                        printf("Lookup named gpio error\n");
-                       return;
+                       return 0;
                }
 
                if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) {
                        printf("gpio request error\n");
-                       return;
+                       return 0;
                }
 
                if (dm_gpio_get_value(&gpio_hw_cfg) == 1)
@@ -77,15 +56,34 @@ static void read_hw_cfg(void)
 
                dm_gpio_free(NULL, &gpio_hw_cfg);
        }
-       printf("0x%02x\n", hw_cfg);
+       return hw_cfg;
 }
 
-static void update_ddr_timings(void)
+static u64 aquila_am69_memory_size(void)
+{
+       u8 hw_cfg = get_hw_cfg();
+
+       switch (hw_cfg & HW_CFG_MEM_CFG_MASK) {
+       case HW_CFG_MEM_SZ_32GB:
+               return SZ_32G;
+       case HW_CFG_MEM_SZ_16GB_RANK_2:
+       case HW_CFG_MEM_SZ_16GB:
+               return SZ_16G;
+       case HW_CFG_MEM_SZ_8GB:
+               return SZ_8G;
+       default:
+               puts("Invalid memory size configuration\n");
+               return -EINVAL;
+       }
+}
+
+#if defined(CONFIG_TARGET_AQUILA_AM69_R5)
+static void update_ddr_timings(u8 hw_cfg)
 {
        int ret = 0;
        void *fdt = (void *)gd->fdt_blob;
 
-       switch (aquila_am69_memory_cfg()) {
+       switch (hw_cfg & HW_CFG_MEM_CFG_MASK) {
        case HW_CFG_MEM_SZ_8GB:
                ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB,
                                                      MULTI_DDR_CFG_INTRLV_SIZE_8GB);
@@ -103,6 +101,7 @@ static void update_ddr_timings(void)
        if (ret)
                printf("Applying DDR patch error: %d\n", ret);
 }
+#endif
 
 static int aquila_am69_fdt_fixup_memory_size(u64 total_sz)
 {
@@ -121,21 +120,33 @@ static int aquila_am69_fdt_fixup_memory_size(u64 total_sz)
        return fdt_fixup_memory_banks(blob, s, e, CONFIG_NR_DRAM_BANKS);
 }
 
+#if defined(CONFIG_TARGET_AQUILA_AM69_R5)
 void do_board_detect(void)
 {
+       u8 hw_cfg;
+
        /* MCU_ADC1 pins used as General Purpose Inputs */
        writel(readl(CTRL_MMR_CFG0_MCU_ADC1_CTRL) | BIT(16),
               CTRL_MMR_CFG0_MCU_ADC1_CTRL);
 
-       read_hw_cfg();
+       hw_cfg = get_hw_cfg();
+       printf("HW CFG: 0x%02x\n", hw_cfg);
 
        if (IS_ENABLED(CONFIG_K3_DDRSS))
-               update_ddr_timings();
+               update_ddr_timings(hw_cfg);
 }
+#endif
+
+#if defined(CONFIG_XPL_BUILD)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
+{
+       fixup_memory_node(spl_image);
+}
+#endif
 
 int dram_init(void)
 {
-       s32 ret;
+       int ret;
 
        ret = fdtdec_setup_mem_size_base_lowest();
        if (ret)
@@ -146,11 +157,18 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-       s32 ret;
+       int ret;
 
-       ret = aquila_am69_fdt_fixup_memory_size(aquila_am69_memory_size());
-       if (ret)
-               printf("Error setting memory size. %d\n", ret);
+       if (IS_ENABLED(CONFIG_SPL_BUILD) &&
+           IS_ENABLED(CONFIG_TARGET_AQUILA_AM69_A72)) {
+               u64 mem_sz = aquila_am69_memory_size();
+
+               ret = aquila_am69_fdt_fixup_memory_size(mem_sz);
+               if (ret)
+                       printf("Error setting memory size. %d\n", ret);
+       } else {
+               fdtdec_setup_mem_size_base();
+       }
 
        ret = fdtdec_setup_memory_banksize();
        if (ret)