realtek: pcs: rtl930x: use generic PLL type definition

Make use of the generic PLL type definition in the current CMU/PLL
configuration code for RTL930x. Assign explicit values to the fields of
the PLL type enum to tie these fields to the values that are used in
the register fields. This allows to simplify the code a bit.

Selecting the PLL to use for a SerDes shares some similarities between
RTL930x and RTL931x. While the location of the selector in the registers
is placed different, similar underlying bit semantics are used. This
allows to reuse the same plain values for both. RTL930x uses a force bit
and a selector bit, RTL931x at least uses the selector bit with the same
values for ring and LC PLL.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
index 12a333635d8fa7a6634d8d76273b79a2744201ec..f3796c984a74e7bb646ab6a4fa769977f8a97930 100644 (file)
--- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
+++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
@@ -98,9 +98,6 @@
 #define RTPCS_930X_SDS_SUBMODE_USXGMII_SX      0x0
 #define RTPCS_930X_SDS_SUBMODE_USXGMII_QX      0x2
 
-#define RTPCS_930X_PLL_LC              0x3
-#define RTPCS_930X_PLL_RING            0x1
-
 /* Registers of the internal SerDes of the 9310 */
 #define RTPCS_931X_MAC_GROUP0_1_CTRL           (0x13a4)
 #define RTPCS_931X_MAC_GROUP2_3_CTRL           (0x13a8)
@@ -150,8 +147,8 @@ enum rtpcs_port_media {
 };
 
 enum rtpcs_sds_pll_type {
-       RTPCS_SDS_PLL_TYPE_RING,
-       RTPCS_SDS_PLL_TYPE_LC,
+       RTPCS_SDS_PLL_TYPE_RING = 0,
+       RTPCS_SDS_PLL_TYPE_LC = 1,
        RTPCS_SDS_PLL_TYPE_END,
 };
 
@@ -1255,7 +1252,9 @@ static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds
         */
 
        pll_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, pbit + 1, pbit);
-       *pll = pll_val == RTPCS_930X_PLL_LC ? RTPCS_SDS_PLL_TYPE_LC : RTPCS_SDS_PLL_TYPE_RING;
+
+       /* bit 0 is force-bit, bit 1 is PLL selector */
+       *pll = (enum rtpcs_sds_pll_type)(pll_val >> 1);
 
        sbit = *pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12;
        speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit);
@@ -1270,7 +1269,6 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_
        struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
        int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12;
        int pbit = (sds == even_sds) ? 4 : 6;
-       int pll_val;
 
        if (speed >= RTPCS_SDS_PLL_SPD_END)
                return -EINVAL;
@@ -1287,9 +1285,10 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_
         * always activate both.
         */
 
-       pll_val = pll == RTPCS_SDS_PLL_TYPE_LC ? RTPCS_930X_PLL_LC : RTPCS_930X_PLL_RING;
        rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf);
-       rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, pll_val);
+
+       /* bit 0 is force-bit, bit 1 is PLL selector */
+       rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, (pll << 1) | BIT(0));
 
        /* bit 0 is force-bit, bits [3:1] are speed selector */
        rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0));