]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/ast: Gen6: Fix open-coded register access
authorThomas Zimmermann <tzimmermann@suse.de>
Fri, 27 Mar 2026 13:33:05 +0000 (14:33 +0100)
committerThomas Zimmermann <tzimmermann@suse.de>
Wed, 8 Apr 2026 09:04:49 +0000 (11:04 +0200)
Replace all open-coded access to MCR and SCU registers in Gen6 with
the appropriate calls to ast_moutdwm() and ast_mindwm(). Use MCR and
SCU register constants. Name variables according to registers.

v2:
- also fix MCR constants

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patch.msgid.link/20260327133532.79696-14-tzimmermann@suse.de
drivers/gpu/drm/ast/ast_2500.c
drivers/gpu/drm/ast/ast_reg.h

index 39f401dd1f4783b8f426800e1d03d44347981c80..03a67ec9684bbf711d01fdea2aab9ff31fd7dc13 100644 (file)
@@ -280,15 +280,13 @@ static void enable_cache_2500(struct ast_device *ast)
 
 static void set_mpll_2500(struct ast_device *ast)
 {
-       u32 addr, data, param;
+       u32 mcr, data, param;
 
        /* Reset MMC */
        ast_moutdwm(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY);
        ast_moutdwm(ast, AST_REG_MCR34, 0x00020080);
-       for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
-               ast_moutdwm(ast, addr, 0x0);
-               addr += 4;
-       }
+       for (mcr = AST_REG_MCR04; mcr <= AST_REG_MCR8C; mcr += 4)
+               ast_moutdwm(ast, mcr, 0x00000000);
        ast_moutdwm(ast, AST_REG_MCR34, 0x00020000);
 
        ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY);
@@ -507,6 +505,8 @@ static void ast_post_chip_2500(struct ast_device *ast)
 
        reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
        if ((reg & AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
+               u32 scu008;
+
                /* Clear bus lock condition */
                ast_2500_patch_ahb(ast->regs);
 
@@ -540,9 +540,9 @@ static void ast_post_chip_2500(struct ast_device *ast)
                        ast_moutdwm(ast, AST_REG_SCU07C, 0x00004000);
 
                /* Slow down CPU/AHB CLK in VGA only mode */
-               temp = ast_read32(ast, 0x12008);
-               temp |= 0x73;
-               ast_write32(ast, 0x12008, temp);
+               scu008 = ast_mindwm(ast, AST_REG_SCU008);
+               scu008 |= 0x00000073;
+               ast_moutdwm(ast, AST_REG_SCU008, scu008);
 
                if (!ast_dram_init_2500(ast))
                        drm_err(dev, "DRAM init failed !\n");
index c3473cad454504b585ae350806875c76c737a9ce..b7259d44a822572aaeb6e6620d098eab6832d04a 100644 (file)
 #define AST_REG_MCR80                          AST_REG_MCR(0x80)
 #define AST_REG_MCR84                          AST_REG_MCR(0x84)
 #define AST_REG_MCR88                          AST_REG_MCR(0x88)
+#define AST_REG_MCR8C                          AST_REG_MCR(0x8c)
 #define AST_REG_MCR100                         AST_REG_MCR(0x100)
 #define AST_REG_MCR108                         AST_REG_MCR(0x108)
 #define AST_REG_MCR120                         AST_REG_MCR(0x120)