]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
hw/misc/aspeed_sdmc: convert to use Resettable interface
authorKane Chen <kane_chen@aspeedtech.com>
Mon, 25 May 2026 04:41:40 +0000 (04:41 +0000)
committerCédric Le Goater <clg@redhat.com>
Tue, 26 May 2026 06:56:48 +0000 (08:56 +0200)
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.

Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-8-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
hw/misc/aspeed_sdmc.c

index 59b4a9a42647349d55205760c1bdd9fec848911f..055abf7f50f0b39ab3a8f86cc40d174b99c82d0b 100644 (file)
@@ -199,9 +199,9 @@ static const MemoryRegionOps aspeed_sdmc_ops = {
     .valid.max_access_size = 4,
 };
 
-static void aspeed_sdmc_reset(DeviceState *dev)
+static void aspeed_sdmc_reset_hold(Object *obj, ResetType type)
 {
-    AspeedSDMCState *s = ASPEED_SDMC(dev);
+    AspeedSDMCState *s = ASPEED_SDMC(obj);
     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 
     memset(s->regs, 0, sizeof(s->regs));
@@ -302,8 +302,9 @@ static const Property aspeed_sdmc_properties[] = {
 static void aspeed_sdmc_class_init(ObjectClass *klass, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     dc->realize = aspeed_sdmc_realize;
-    device_class_set_legacy_reset(dc, aspeed_sdmc_reset);
+    rc->phases.hold = aspeed_sdmc_reset_hold;
     dc->desc = "ASPEED SDRAM Memory Controller";
     dc->vmsd = &vmstate_aspeed_sdmc;
     device_class_set_props(dc, aspeed_sdmc_properties);
@@ -560,9 +561,9 @@ static const TypeInfo aspeed_2600_sdmc_info = {
     .class_init = aspeed_2600_sdmc_class_init,
 };
 
-static void aspeed_2700_sdmc_reset(DeviceState *dev)
+static void aspeed_2700_sdmc_reset_hold(Object *obj, ResetType type)
 {
-    AspeedSDMCState *s = ASPEED_SDMC(dev);
+    AspeedSDMCState *s = ASPEED_SDMC(obj);
     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 
     memset(s->regs, 0, sizeof(s->regs));
@@ -676,10 +677,11 @@ static const uint64_t
 static void aspeed_2700_sdmc_class_init(ObjectClass *klass, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
 
     dc->desc = "ASPEED 2700 SDRAM Memory Controller";
-    device_class_set_legacy_reset(dc, aspeed_2700_sdmc_reset);
+    rc->phases.hold = aspeed_2700_sdmc_reset_hold;
 
     asc->is_bus64bit = true;
     asc->max_ram_size = 8 * GiB;