drm/i915/dsi: Track the detailed DSC slice configuration

Add tracking for the DSI DSC pipes-per-line and slices-per-stream value
in the slice config state and compute the current slices-per-line value
using this slice config state. The slices-per-line value used atm will
be removed by a follow-up change after converting all the places using
it to use the detailed slice config instead.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260114162232.92731-5-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 9b4428472831824b33457609174cb228b01e4a7e..8fcfdb2e1c74e6e8c40f8a91fa7e8b24297499ac 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -41,6 +41,7 @@
 #include "intel_display_utils.h"
 #include "intel_gmbus.h"
 #include "intel_rom.h"
+#include "intel_vdsc.h"
 
 #define _INTEL_BIOS_PRIVATE
 #include "intel_vbt_defs.h"
@@ -3578,12 +3579,14 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
         *
         * FIXME: split only when necessary
         */
+       crtc_state->dsc.slice_config.pipes_per_line = 1;
+
        if (dsc->slices_per_line & BIT(2)) {
                crtc_state->dsc.slice_config.streams_per_pipe = 2;
-               crtc_state->dsc.slice_count = 4;
+               crtc_state->dsc.slice_config.slices_per_stream = 2;
        } else if (dsc->slices_per_line & BIT(1)) {
                crtc_state->dsc.slice_config.streams_per_pipe = 2;
-               crtc_state->dsc.slice_count = 2;
+               crtc_state->dsc.slice_config.slices_per_stream = 1;
        } else {
                /* FIXME */
                if (!(dsc->slices_per_line & BIT(0)))
@@ -3591,9 +3594,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
                                    "VBT: Unsupported DSC slice count for DSI\n");
 
                crtc_state->dsc.slice_config.streams_per_pipe = 1;
-               crtc_state->dsc.slice_count = 1;
+               crtc_state->dsc.slice_config.slices_per_stream = 1;
        }
 
+       crtc_state->dsc.slice_count = intel_dsc_line_slice_count(&crtc_state->dsc.slice_config);
+
        if (crtc_state->hw.adjusted_mode.crtc_hdisplay %
            crtc_state->dsc.slice_count != 0)
                drm_dbg_kms(display->drm,