spi: tegra114: Preserve SPI mode bits in def_command1_reg

[ Upstream commit a0a75b40c919b9f6d3a0b6c978e6ccf344c1be5a ]

The COMMAND1 register bits [29:28] set the SPI mode, which controls
the clock idle level. When a transfer ends, tegra_spi_transfer_end()
writes def_command1_reg back to restore the default state, but this
register value currently lacks the mode bits. This results in the
clock always being configured as idle low, breaking devices that
need it high.

Fix this by storing the mode bits in def_command1_reg during setup,
to prevent this field from always being cleared.

Fixes: f333a331adfa ("spi/tegra114: add spi driver")
Signed-off-by: Vishwaroop A <va@nvidia.com>
Link: https://patch.msgid.link/20260204141212.1540382-1-va@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 795a8482c2c700c3768bd50bf59971256893a486..48fb11fea55f2de82a818dc09ffa4474e674bce9 100644 (file)
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -978,11 +978,14 @@ static int tegra_spi_setup(struct spi_device *spi)
        if (spi_get_csgpiod(spi, 0))
                gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
 
+       /* Update default register to include CS polarity and SPI mode */
        val = tspi->def_command1_reg;
        if (spi->mode & SPI_CS_HIGH)
                val &= ~SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
        else
                val |= SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
+       val &= ~SPI_CONTROL_MODE_MASK;
+       val |= SPI_MODE_SEL(spi->mode & 0x3);
        tspi->def_command1_reg = val;
        tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
        spin_unlock_irqrestore(&tspi->lock, flags);