coco/tdx-host: Don't expose P-SEAMLDR information on CPUs with erratum

TDX-capable CPUs clobber the current VMCS on P-SEAMLDR calls. Clearing
the current VMCS behind KVM's back breaks KVM.

Future CPUs will fix this by preserving the current VMCS across
P-SEAMLDR calls. A future specification update will describe the
VMCS-clearing behavior as an erratum and to state that it does not
occur when IA32_VMX_BASIC[60] is set.

Add a CPU bug bit and refuse to expose P-SEAMLDR information on
affected CPUs.

Use a CPU bug bit to stay consistent with X86_BUG_TDX_PW_MCE. As a
bonus, the bug bit is visible to userspace, which allows userspace to
determine why these sysfs files are not exposed, and it can also be
checked by other kernel components in the future if needed.

== Alternatives ==
Two workarounds were considered but both were rejected:

1. Save/restore the current VMCS around P-SEAMLDR calls. This produces ugly
   assembly code [1] and doesn't play well with #MCE or #NMI if they
   need to use the current VMCS.

2. Move KVM's VMCS tracking logic to the TDX core code, which would break
   the boundary between KVM and the TDX core code [2].

[ dhansen: comment and changelog munging. Add seamldr_call() bug check. ]

Signed-off-by: Chao Gao <chao.gao@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Kai Huang <kai.huang@intel.com>
Reviewed-by: Kiryl Shutsemau (Meta) <kas@kernel.org>
Reviewed-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/kvm/fedb3192-e68c-423c-93b2-a4dc2f964148@intel.com/
Link: https://lore.kernel.org/kvm/aYIXFmT-676oN6j0@google.com/
Link: https://patch.msgid.link/20260520133909.409394-12-chao.gao@intel.com

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 1d506e5d6f46acda118ce1e99468351b8c55e827..7b572bc24265cd8d458e8818f98e43b264eb6c2a 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -573,4 +573,5 @@
 #define X86_BUG_ITS_NATIVE_ONLY                X86_BUG( 1*32+ 8) /* "its_native_only" CPU is affected by ITS, VMX is not affected */
 #define X86_BUG_TSA                    X86_BUG( 1*32+ 9) /* "tsa" CPU is affected by Transient Scheduler Attacks */
 #define X86_BUG_VMSCAPE                        X86_BUG( 1*32+10) /* "vmscape" CPU is affected by VMSCAPE attacks from guests */
+#define X86_BUG_SEAMRET_INVD_VMCS      X86_BUG( 1*32+11) /* "seamret_invd_vmcs" SEAMRET from P-SEAMLDR clears the current VMCS */
 #endif /* _ASM_X86_CPUFEATURES_H */

diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 37080382df54865d352415266e8c5a8330236c3c..49d8551d285d98ea398b7bda74b90867132d8b3a 100644 (file)
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -147,6 +147,7 @@ struct vmcs {
 #define VMX_BASIC_INOUT                                BIT_ULL(54)
 #define VMX_BASIC_TRUE_CTLS                    BIT_ULL(55)
 #define VMX_BASIC_NO_HW_ERROR_CODE_CC          BIT_ULL(56)
+#define VMX_BASIC_NO_SEAMRET_INVD_VMCS         BIT_ULL(60)
 
 static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
 {

diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamldr.c
index 7269a239bc225df155db91261bd53e100229b535..baa86f2da04ebad04f0a851a20d7e9e4c0d0dd4b 100644 (file)
--- a/arch/x86/virt/vmx/tdx/seamldr.c
+++ b/arch/x86/virt/vmx/tdx/seamldr.c
@@ -6,8 +6,11 @@
  */
 #define pr_fmt(fmt)    "seamldr: " fmt
 
+#include <linux/bug.h>
 #include <linux/spinlock.h>
 
+#include <asm/cpufeature.h>
+#include <asm/cpufeatures.h>
 #include <asm/seamldr.h>
 
 #include "seamcall_internal.h"
@@ -25,6 +28,16 @@ static DEFINE_RAW_SPINLOCK(seamldr_lock);
 
 static int seamldr_call(u64 fn, struct tdx_module_args *args)
 {
+       /*
+        * With this bug, P-SEAMLDR calls corrupt the VMCS
+        * pointer and must be avoided. This path should be
+        * unreachable since sysfs hides the ABIs.
+        */
+       if (boot_cpu_has_bug(X86_BUG_SEAMRET_INVD_VMCS)) {
+               WARN_ON(1);
+               return -EINVAL;
+       }
+
        guard(raw_spinlock)(&seamldr_lock);
        return seamcall_prerr(fn, args);
 }

diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c
index 5fb0441a9ac6ce49df0a7ef9c5a502aa6fdfd670..53cf99c41dbbf7151976d38ca6a0bb226555bace 100644 (file)
--- a/arch/x86/virt/vmx/tdx/tdx.c
+++ b/arch/x86/virt/vmx/tdx/tdx.c
@@ -42,6 +42,7 @@
 #include <asm/processor.h>
 #include <asm/mce.h>
 #include <asm/virt.h>
+#include <asm/vmx.h>
 
 #include "seamcall_internal.h"
 #include "tdx.h"
@@ -1450,6 +1451,8 @@ static struct notifier_block tdx_memory_nb = {
 
 static void __init check_tdx_erratum(void)
 {
+       u64 basic_msr;
+
        /*
         * These CPUs have an erratum.  A partial write from non-TD
         * software (e.g. via MOVNTI variants or UC/WC mapping) to TDX
@@ -1461,6 +1464,14 @@ static void __init check_tdx_erratum(void)
        case INTEL_EMERALDRAPIDS_X:
                setup_force_cpu_bug(X86_BUG_TDX_PW_MCE);
        }
+
+       /*
+        * Some TDX-capable CPUs have an erratum where the current VMCS is
+        * cleared after calling into P-SEAMLDR.
+        */
+       rdmsrq(MSR_IA32_VMX_BASIC, basic_msr);
+       if (!(basic_msr & VMX_BASIC_NO_SEAMRET_INVD_VMCS))
+               setup_force_cpu_bug(X86_BUG_SEAMRET_INVD_VMCS);
 }
 
 void __init tdx_init(void)

diff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-host/tdx-host.c
index 2997311f72fa8908d30be1fc9733a6e9923f0aad..2886554f0e60068961df56791c6db454382e750e 100644 (file)
--- a/drivers/virt/coco/tdx-host/tdx-host.c
+++ b/drivers/virt/coco/tdx-host/tdx-host.c
@@ -98,6 +98,14 @@ static umode_t seamldr_group_visible(struct kobject *kobj, struct attribute *att
        if (!tdx_supports_runtime_update(sysinfo))
                return 0;
 
+       /*
+        * This bug makes P-SEAMLDR calls clobber the current VMCS
+        * which breaks KVM. Avoid P-SEAMLDR calls by hiding all
+        * attributes if the CPU has this bug.
+        */
+       if (boot_cpu_has_bug(X86_BUG_SEAMRET_INVD_VMCS))
+               return 0;
+
        return attr->mode;
 }