arm64: dts: renesas: Update reset IDs on R-Car Gen5 R8A78000 X5H

The current DT reset ID encoding in R-Car Gen5 R8A78000 X5H U-Boot DTs
is inherited from downstream BSP. New reset bindings for this SoC are
now submitted and under review [1]. Replace the DT reset IDs with the
ones used in the new bindings.

[1] https://lore.kernel.org/all/053c312d07445517d8f9c84bfe3cc8fb72d4cd9a.1776793163.git.geert+renesas@glider.be/

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/include/dt-bindings/reset/r8a78000-reset-scmi.h b/include/dt-bindings/reset/r8a78000-reset-scmi.h
index e0d10caa589b1a30a13af13af54304c7b25e5ffa..3d84bfb073af6597479663f9af6d09e3e9763495 100644 (file)
--- a/include/dt-bindings/reset/r8a78000-reset-scmi.h
+++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h
@@ -1,33 +1,27 @@
 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 /*
- * Copyright (C) 2025 Renesas Electronics Corp.
- *
- * IDs match SCP 4.27
+ * Copyright (C) 2025-2026 Renesas Electronics Corp.
  */
 
 #ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__
 #define __DT_BINDINGS_R8A78000_SCMI_RESET_H__
 
-/*
- * These definition indices match the Reset ID defined by SCP FW 4.27.
- */
-
-#define SCP_RESET_DOMAIN_ID_UFS0       202
-#define SCP_RESET_DOMAIN_ID_UFS1       203
+#define SCP_RESET_DOMAIN_ID_UFS0       0x60
+#define SCP_RESET_DOMAIN_ID_UFS1       0x61
 
-#define SCP_RESET_DOMAIN_ID_XPCS0      316
-#define SCP_RESET_DOMAIN_ID_XPCS1      317
-#define SCP_RESET_DOMAIN_ID_XPCS2      318
-#define SCP_RESET_DOMAIN_ID_XPCS3      319
-#define SCP_RESET_DOMAIN_ID_XPCS4      320
-#define SCP_RESET_DOMAIN_ID_XPCS5      321
-#define SCP_RESET_DOMAIN_ID_XPCS6      322
-#define SCP_RESET_DOMAIN_ID_XPCS7      323
+#define SCP_RESET_DOMAIN_ID_XPCS0      0x30
+#define SCP_RESET_DOMAIN_ID_XPCS1      0x31
+#define SCP_RESET_DOMAIN_ID_XPCS2      0x32
+#define SCP_RESET_DOMAIN_ID_XPCS3      0x33
+#define SCP_RESET_DOMAIN_ID_XPCS4      0x34
+#define SCP_RESET_DOMAIN_ID_XPCS5      0x35
+#define SCP_RESET_DOMAIN_ID_XPCS6      0x36
+#define SCP_RESET_DOMAIN_ID_XPCS7      0x37
 
-#define SCP_RESET_DOMAIN_ID_MPPHY01    344
-#define SCP_RESET_DOMAIN_ID_MPPHY11    345
-#define SCP_RESET_DOMAIN_ID_MPPHY21    346
-#define SCP_RESET_DOMAIN_ID_MPPHY31    347
-#define SCP_RESET_DOMAIN_ID_MPPHY02    348
+#define SCP_RESET_DOMAIN_ID_MPPHY01    0x64
+#define SCP_RESET_DOMAIN_ID_MPPHY11    0x65
+#define SCP_RESET_DOMAIN_ID_MPPHY21    0x66
+#define SCP_RESET_DOMAIN_ID_MPPHY31    0x67
+#define SCP_RESET_DOMAIN_ID_MPPHY02    0x68
 
 #endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */