phy: ti: phy-j721e-wiz: add support for J722S SoC family

The J722S WIZ is mostly identical to the AM64's, but additionally supports
SGMII.

Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
Link: https://patch.msgid.link/85e9f67f8673dc7039ab87c34cfc9e4de1c7447c.1775559102.git.nora.schiffer@ew.tq-group.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 6b584706b913af0bb8d1c94fade2b3b857d9ffc2..7531a8a0491239b70fe32477af04ebdc5a03be0d 100644 (file)
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -331,6 +331,7 @@ enum wiz_type {
        J721E_WIZ_16G,
        J721E_WIZ_10G,  /* Also for J7200 SR1.0 */
        AM64_WIZ_10G,
+       J722S_WIZ_10G,
        J7200_WIZ_10G,  /* J7200 SR2.0 */
        J784S4_WIZ_10G,
        J721S2_WIZ_10G,
@@ -1020,6 +1021,7 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
 
        switch (wiz->type) {
        case AM64_WIZ_10G:
+       case J722S_WIZ_10G:
        case J7200_WIZ_10G:
        case J784S4_WIZ_10G:
        case J721S2_WIZ_10G:
@@ -1089,6 +1091,7 @@ static void wiz_clock_init(struct wiz *wiz)
 
        switch (wiz->type) {
        case AM64_WIZ_10G:
+       case J722S_WIZ_10G:
        case J7200_WIZ_10G:
                switch (rate) {
                case REF_CLK_100MHZ:
@@ -1158,6 +1161,7 @@ static int wiz_clock_probe(struct wiz *wiz, struct device_node *node)
 
        switch (wiz->type) {
        case AM64_WIZ_10G:
+       case J722S_WIZ_10G:
        case J7200_WIZ_10G:
        case J784S4_WIZ_10G:
        case J721S2_WIZ_10G:
@@ -1246,6 +1250,14 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
                if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
                        return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
                break;
+
+       case J722S_WIZ_10G:
+               if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
+                       return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+               if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
+                       return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
+               break;
+
        default:
                return 0;
        }
@@ -1350,6 +1362,15 @@ static struct wiz_data am64_10g_data = {
        .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
 };
 
+static struct wiz_data j722s_10g_data = {
+       .type = J722S_WIZ_10G,
+       .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+       .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
+       .refclk_dig_sel = &refclk_dig_sel_10g,
+       .clk_mux_sel = clk_mux_sel_10g,
+       .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
 static struct wiz_data j7200_pg2_10g_data = {
        .type = J7200_WIZ_10G,
        .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel,
@@ -1389,6 +1410,9 @@ static const struct of_device_id wiz_id_table[] = {
        {
                .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
        },
+       {
+               .compatible = "ti,j722s-wiz-10g", .data = &j722s_10g_data,
+       },
        {
                .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
        },