#include <linux/regmap.h>
#include <linux/types.h>
-#define RTMDIO_MAX_PORTS 57
-#define RTMDIO_MAX_SMI_BUSSES 4
-
-#define RTMDIO_838X_NUM_BUSSES 1
-#define RTMDIO_838X_NUM_PAGES 4096
-#define RTMDIO_838X_NUM_PORTS 28
-#define RTMDIO_839X_NUM_BUSSES 2
-#define RTMDIO_839X_NUM_PAGES 8192
-#define RTMDIO_839X_NUM_PORTS 52
-#define RTMDIO_930X_NUM_BUSSES 4
-#define RTMDIO_930X_NUM_PAGES 4096
-#define RTMDIO_930X_NUM_PORTS 28
-#define RTMDIO_931X_NUM_BUSSES 4
-#define RTMDIO_931X_NUM_PAGES 8192
-#define RTMDIO_931X_NUM_PORTS 56
-
-#define RTMDIO_PAGE_SELECT 0x1f
-#define RTMDIO_RAW_PAGE(p) ((p) - 1)
-
-#define RTMDIO_PHY_AQR113C_A 0x31c31c12
-#define RTMDIO_PHY_AQR113C_B 0x31c31c13
-#define RTMDIO_PHY_AQR813 0x31c31cb2
-#define RTMDIO_PHY_RTL8218D 0x001cc983
-#define RTMDIO_PHY_RTL8218E 0x001cc984
-#define RTMDIO_PHY_RTL8221B_VB_CG 0x001cc849
-#define RTMDIO_PHY_RTL8221B_VM_CG 0x001cc84a
-#define RTMDIO_PHY_RTL8224 0x001ccad0
-#define RTMDIO_PHY_RTL8226 0x001cc838
-#define RTMDIO_PHY_RTL8261 0x001ccaf3
-
-#define RTMDIO_PHY_MAC_1G 3
-#define RTMDIO_PHY_MAC_2G_PLUS 1
-#define RTMDIO_PHY_MAC_SDS 0
-
-#define RTMDIO_PHY_POLL_MMD(dev, reg, bit) ((((bit) & GENMASK(3, 0)) << 21) | \
+#define RTMD_MAX_PORTS 57
+#define RTMD_MAX_SMI_BUSSES 4
+
+#define RTMD_838X_NUM_BUSSES 1
+#define RTMD_838X_NUM_PAGES 4096
+#define RTMD_838X_NUM_PORTS 28
+#define RTMD_839X_NUM_BUSSES 2
+#define RTMD_839X_NUM_PAGES 8192
+#define RTMD_839X_NUM_PORTS 52
+#define RTMD_930X_NUM_BUSSES 4
+#define RTMD_930X_NUM_PAGES 4096
+#define RTMD_930X_NUM_PORTS 28
+#define RTMD_931X_NUM_BUSSES 4
+#define RTMD_931X_NUM_PAGES 8192
+#define RTMD_931X_NUM_PORTS 56
+
+#define RTMD_PAGE_SELECT 0x1f
+#define RTMD_RAW_PAGE(p) ((p) - 1)
+
+#define RTMD_PHY_AQR113C_A 0x31c31c12
+#define RTMD_PHY_AQR113C_B 0x31c31c13
+#define RTMD_PHY_AQR813 0x31c31cb2
+#define RTMD_PHY_RTL8218D 0x001cc983
+#define RTMD_PHY_RTL8218E 0x001cc984
+#define RTMD_PHY_RTL8221B_VB_CG 0x001cc849
+#define RTMD_PHY_RTL8221B_VM_CG 0x001cc84a
+#define RTMD_PHY_RTL8224 0x001ccad0
+#define RTMD_PHY_RTL8226 0x001cc838
+#define RTMD_PHY_RTL8261 0x001ccaf3
+
+#define RTMD_PHY_MAC_1G 3
+#define RTMD_PHY_MAC_2G_PLUS 1
+#define RTMD_PHY_MAC_SDS 0
+
+#define RTMD_PHY_POLL_MMD(dev, reg, bit) ((((bit) & GENMASK(3, 0)) << 21) | \
(((dev) & GENMASK(4, 0)) << 16) | \
((reg) & GENMASK(15, 0)))
/* MDIO bus registers/fields */
-#define RTMDIO_C45_DATA(devnum, regnum) ((((devnum) & GENMASK(4, 0)) << 16) | \
+#define RTMD_C45_DATA(devnum, regnum) ((((devnum) & GENMASK(4, 0)) << 16) | \
((regnum) & GENMASK(15, 0)))
-#define RTMDIO_DATA_IN_HI_OUT_LOW 16
-#define RTMDIO_DATA_IN_LOW_OUT_HI 0
-#define RTMDIO_RUN BIT(0)
-
-#define RTMDIO_838X_SMI_GLB_CTRL 0xa100
-#define RTMDIO_838X_SMI_GLB_PHY_MAN_24_27 BIT(7)
-#define RTMDIO_838X_SMI_GLB_PHY_PATCH_DONE BIT(15)
-#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0 0xa1b8
-#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1 0xa1bc
-#define RTMDIO_838X_CMD_FAIL 0 /* No hardware support */
-#define RTMDIO_838X_CMD_READ_C22 0
-#define RTMDIO_838X_CMD_READ_C45 BIT(1)
-#define RTMDIO_838X_CMD_WRITE_C22 BIT(2)
-#define RTMDIO_838X_CMD_WRITE_C45 (BIT(1) | BIT(2))
-#define RTMDIO_838X_C22_DATA(page, reg) ((reg) << 20 | RTMDIO_PAGE_SELECT << 15 | (page) << 3)
-#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2 0xa1c0
-#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3 0xa1c4
-#define RTMDIO_838X_SMI_POLL_CTRL 0xa17c
-#define RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL 0xa1c8
-
-#define RTMDIO_839X_BCAST_PHYID_CTRL 0x03ec
-#define RTMDIO_839X_PHYREG_ACCESS_CTRL 0x03dc
-#define RTMDIO_839X_CMD_FAIL BIT(1)
-#define RTMDIO_839X_CMD_READ_C22 0
-#define RTMDIO_839X_CMD_READ_C45 BIT(2)
-#define RTMDIO_839X_CMD_WRITE_C22 BIT(3)
-#define RTMDIO_839X_CMD_WRITE_C45 (BIT(2) | BIT(3))
-#define RTMDIO_839X_C22_DATA(page, reg) ((reg) << 5 | (page) << 10)
-#define RTMDIO_839X_PHYREG_CTRL (0x03e0)
-#define RTMDIO_839X_PHYREG_SKIP_EXT_PAGE GENMASK(8, 0)
-#define RTMDIO_839X_PHYREG_DATA_CTRL 0x03f0
-#define RTMDIO_839X_PHYREG_MMD_CTRL 0x03f4
-#define RTMDIO_839X_PHYREG_PORT_CTRL(x) (0x03e4 + (x) * 4)
-#define RTMDIO_839X_SMI_PORT_POLLING_CTRL 0x03fc
-#define RTMDIO_839X_SMI_GLB_CTRL 0x03f8
-
-#define RTMDIO_930X_SMI_GLB_CTRL 0xca00
-#define RTMDIO_930X_SMI_GLB_INTF_SEL(bus) BIT(16 + (bus))
-#define RTMDIO_930X_SMI_GLB_POLL_SEL(bus) BIT(20 + (bus))
-#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0 0xcb70
-#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1 0xcb74
-#define RTMDIO_930X_CMD_FAIL BIT(25)
-#define RTMDIO_930X_CMD_READ_C22 0
-#define RTMDIO_930X_CMD_READ_C45 BIT(1)
-#define RTMDIO_930X_CMD_WRITE_C22 BIT(2)
-#define RTMDIO_930X_CMD_WRITE_C45 (BIT(1) | BIT(2))
-#define RTMDIO_930X_C22_DATA(page, reg) ((reg) << 20 | RTMDIO_PAGE_SELECT << 15 | (page) << 3)
-#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2 0xcb78
-#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3 0xcb7c
-#define RTMDIO_930X_SMI_PORT0_15_POLLING_SEL 0xca08
-#define RTMDIO_930X_SMI_PORT16_27_POLLING_SEL 0xca0c
-#define RTMDIO_930X_SMI_MAC_TYPE_CTRL 0xca04
-#define RTMDIO_930X_SMI_MAC_TYPE_P0_23(pn) (GENMASK(1, 0) << (((pn) / 4) * 2))
-#define RTMDIO_930X_SMI_MAC_TYPE_P24_27(pn) (GENMASK(2, 0) << (((pn) - 24) * 3 + 12))
-#define RTMDIO_930X_SMI_POLL_CTRL 0xca90
-#define RTMDIO_930X_SMI_PRVTE_POLLING_CTRL 0xca10
-#define RTMDIO_930X_SMI_10G_POLLING_REG0_CFG 0xcbb4
-#define RTMDIO_930X_SMI_10G_POLLING_REG9_CFG 0xcbb8
-#define RTMDIO_930X_SMI_10G_POLLING_REG10_CFG 0xcbbc
-#define RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL 0xcb80
-
-#define RTMDIO_931X_SMI_PORT_POLLING_CTRL 0x0ccc
-#define RTMDIO_931X_SMI_INDRT_ACCESS_BC 0x0c14
-#define RTMDIO_931X_SMI_INDRT_PORT(pn) ((pn) << 5)
-#define RTMDIO_931X_SMI_GLB_CTRL0 0x0cc0
-#define RTMDIO_931X_SMI_GLB_PRVTE0_POLL(bus) BIT(20 + (bus))
-#define RTMDIO_931X_SMI_GLB_PRVTE1_POLL(bus) BIT(24 + (bus))
-#define RTMDIO_931X_SMI_GLB_CTRL1 0x0cbc
-#define RTMDIO_931X_SMI_GLB_FMT_SEL_C45(bus) BIT((bus) * 2 + 1)
-#define RTMDIO_931X_SMI_GLB_FMT_SEL_FRC(bus) BIT((bus) * 2)
-#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0 0x0c00
-#define RTMDIO_931X_CMD_FAIL BIT(1)
-#define RTMDIO_931X_CMD_READ_C22 0
-#define RTMDIO_931X_CMD_READ_C45 BIT(3)
-#define RTMDIO_931X_CMD_WRITE_C22 BIT(4)
-#define RTMDIO_931X_CMD_WRITE_C45 (BIT(3) | BIT(4))
-#define RTMDIO_931X_C22_DATA(page, reg) ((reg) << 6 | (page) << 11)
-#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1 0x0c04
-#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2(x) (0x0c08 + (x) * 4)
-#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3 0x0c10
-#define RTMDIO_931X_SMI_INDRT_ACCESS_MMD 0x0c18
-#define RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL(pn) (0x0cac + ((pn) / 16) * 4)
-#define RTMDIO_931X_SMI_PHY_ABLTY_MDIO 0x0
-#define RTMDIO_931X_SMI_PHY_ABLTY_SDS 0x2
-#define RTMDIO_931X_SMI_PHY_ABLTY_MASK(pn) (GENMASK(1, 0) << (((pn) % 16) * 2))
-#define RTMDIO_931X_SMI_PORT_POLLING_SEL 0x0c9c
-#define RTMDIO_931X_SMI_PORT_ADDR_CTRL 0x0c74
-#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL0 0x0cf0
-#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL1 0x0cf4
-#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL2 0x0cf8
-#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL3 0x0cfc
-#define RTMDIO_931X_SMI_10GPHY_POLLING_SEL4 0x0d00
+#define RTMD_DATA_IN_HI_OUT_LOW 16
+#define RTMD_DATA_IN_LOW_OUT_HI 0
+#define RTMD_RUN BIT(0)
+
+#define RTMD_838X_SMI_GLB_CTRL 0xa100
+#define RTMD_838X_SMI_GLB_PHY_MAN_24_27 BIT(7)
+#define RTMD_838X_SMI_GLB_PHY_PATCH_DONE BIT(15)
+#define RTMD_838X_SMI_ACCESS_PHY_CTRL_0 0xa1b8
+#define RTMD_838X_SMI_ACCESS_PHY_CTRL_1 0xa1bc
+#define RTMD_838X_CMD_FAIL 0 /* No hardware support */
+#define RTMD_838X_CMD_READ_C22 0
+#define RTMD_838X_CMD_READ_C45 BIT(1)
+#define RTMD_838X_CMD_WRITE_C22 BIT(2)
+#define RTMD_838X_CMD_WRITE_C45 (BIT(1) | BIT(2))
+#define RTMD_838X_C22_DATA(page, reg) ((reg) << 20 | RTMD_PAGE_SELECT << 15 | (page) << 3)
+#define RTMD_838X_SMI_ACCESS_PHY_CTRL_2 0xa1c0
+#define RTMD_838X_SMI_ACCESS_PHY_CTRL_3 0xa1c4
+#define RTMD_838X_SMI_POLL_CTRL 0xa17c
+#define RTMD_838X_SMI_PORT0_5_ADDR_CTRL 0xa1c8
+
+#define RTMD_839X_BCAST_PHYID_CTRL 0x03ec
+#define RTMD_839X_PHYREG_ACCESS_CTRL 0x03dc
+#define RTMD_839X_CMD_FAIL BIT(1)
+#define RTMD_839X_CMD_READ_C22 0
+#define RTMD_839X_CMD_READ_C45 BIT(2)
+#define RTMD_839X_CMD_WRITE_C22 BIT(3)
+#define RTMD_839X_CMD_WRITE_C45 (BIT(2) | BIT(3))
+#define RTMD_839X_C22_DATA(page, reg) ((reg) << 5 | (page) << 10)
+#define RTMD_839X_PHYREG_CTRL (0x03e0)
+#define RTMD_839X_PHYREG_SKIP_EXT_PAGE GENMASK(8, 0)
+#define RTMD_839X_PHYREG_DATA_CTRL 0x03f0
+#define RTMD_839X_PHYREG_MMD_CTRL 0x03f4
+#define RTMD_839X_PHYREG_PORT_CTRL(x) (0x03e4 + (x) * 4)
+#define RTMD_839X_SMI_PORT_POLLING_CTRL 0x03fc
+#define RTMD_839X_SMI_GLB_CTRL 0x03f8
+
+#define RTMD_930X_SMI_GLB_CTRL 0xca00
+#define RTMD_930X_SMI_GLB_INTF_SEL(bus) BIT(16 + (bus))
+#define RTMD_930X_SMI_GLB_POLL_SEL(bus) BIT(20 + (bus))
+#define RTMD_930X_SMI_ACCESS_PHY_CTRL_0 0xcb70
+#define RTMD_930X_SMI_ACCESS_PHY_CTRL_1 0xcb74
+#define RTMD_930X_CMD_FAIL BIT(25)
+#define RTMD_930X_CMD_READ_C22 0
+#define RTMD_930X_CMD_READ_C45 BIT(1)
+#define RTMD_930X_CMD_WRITE_C22 BIT(2)
+#define RTMD_930X_CMD_WRITE_C45 (BIT(1) | BIT(2))
+#define RTMD_930X_C22_DATA(page, reg) ((reg) << 20 | RTMD_PAGE_SELECT << 15 | (page) << 3)
+#define RTMD_930X_SMI_ACCESS_PHY_CTRL_2 0xcb78
+#define RTMD_930X_SMI_ACCESS_PHY_CTRL_3 0xcb7c
+#define RTMD_930X_SMI_PORT0_15_POLLING_SEL 0xca08
+#define RTMD_930X_SMI_PORT16_27_POLLING_SEL 0xca0c
+#define RTMD_930X_SMI_MAC_TYPE_CTRL 0xca04
+#define RTMD_930X_SMI_MAC_TYPE_P0_23(pn) (GENMASK(1, 0) << (((pn) / 4) * 2))
+#define RTMD_930X_SMI_MAC_TYPE_P24_27(pn) (GENMASK(2, 0) << (((pn) - 24) * 3 + 12))
+#define RTMD_930X_SMI_POLL_CTRL 0xca90
+#define RTMD_930X_SMI_PRVTE_POLLING_CTRL 0xca10
+#define RTMD_930X_SMI_10G_POLLING_REG0_CFG 0xcbb4
+#define RTMD_930X_SMI_10G_POLLING_REG9_CFG 0xcbb8
+#define RTMD_930X_SMI_10G_POLLING_REG10_CFG 0xcbbc
+#define RTMD_930X_SMI_PORT0_5_ADDR_CTRL 0xcb80
+
+#define RTMD_931X_SMI_PORT_POLLING_CTRL 0x0ccc
+#define RTMD_931X_SMI_INDRT_ACCESS_BC 0x0c14
+#define RTMD_931X_SMI_INDRT_PORT(pn) ((pn) << 5)
+#define RTMD_931X_SMI_GLB_CTRL0 0x0cc0
+#define RTMD_931X_SMI_GLB_PRVTE0_POLL(bus) BIT(20 + (bus))
+#define RTMD_931X_SMI_GLB_PRVTE1_POLL(bus) BIT(24 + (bus))
+#define RTMD_931X_SMI_GLB_CTRL1 0x0cbc
+#define RTMD_931X_SMI_GLB_FMT_SEL_C45(bus) BIT((bus) * 2 + 1)
+#define RTMD_931X_SMI_GLB_FMT_SEL_FRC(bus) BIT((bus) * 2)
+#define RTMD_931X_SMI_INDRT_ACCESS_CTRL_0 0x0c00
+#define RTMD_931X_CMD_FAIL BIT(1)
+#define RTMD_931X_CMD_READ_C22 0
+#define RTMD_931X_CMD_READ_C45 BIT(3)
+#define RTMD_931X_CMD_WRITE_C22 BIT(4)
+#define RTMD_931X_CMD_WRITE_C45 (BIT(3) | BIT(4))
+#define RTMD_931X_C22_DATA(page, reg) ((reg) << 6 | (page) << 11)
+#define RTMD_931X_SMI_INDRT_ACCESS_CTRL_1 0x0c04
+#define RTMD_931X_SMI_INDRT_ACCESS_CTRL_2(x) (0x0c08 + (x) * 4)
+#define RTMD_931X_SMI_INDRT_ACCESS_CTRL_3 0x0c10
+#define RTMD_931X_SMI_INDRT_ACCESS_MMD 0x0c18
+#define RTMD_931X_SMI_PHY_ABLTY_GET_SEL(pn) (0x0cac + ((pn) / 16) * 4)
+#define RTMD_931X_SMI_PHY_ABLTY_MDIO 0x0
+#define RTMD_931X_SMI_PHY_ABLTY_SDS 0x2
+#define RTMD_931X_SMI_PHY_ABLTY_MASK(pn) (GENMASK(1, 0) << (((pn) % 16) * 2))
+#define RTMD_931X_SMI_PORT_POLLING_SEL 0x0c9c
+#define RTMD_931X_SMI_PORT_ADDR_CTRL 0x0c74
+#define RTMD_931X_SMI_10GPHY_POLLING_SEL0 0x0cf0
+#define RTMD_931X_SMI_10GPHY_POLLING_SEL1 0x0cf4
+#define RTMD_931X_SMI_10GPHY_POLLING_SEL2 0x0cf8
+#define RTMD_931X_SMI_10GPHY_POLLING_SEL3 0x0cfc
+#define RTMD_931X_SMI_10GPHY_POLLING_SEL4 0x0d00
#define for_each_port(ctrl, pn) \
- for_each_set_bit(pn, (ctrl)->valid_ports, RTMDIO_MAX_PORTS)
+ for_each_set_bit(pn, (ctrl)->valid_ports, RTMD_MAX_PORTS)
/*
* On all Realtek switch platforms the hardware periodically reads the link status of all
* the accesses and the state of the bus with the attributes page[], raw[] and portaddr
* of the bus_priv structure. The page selection works as follows:
*
- * phy_write(phydev, RTMDIO_PAGE_SELECT, 12) : store internal page 12 in driver
+ * phy_write(phydev, RTMD_PAGE_SELECT, 12) : store internal page 12 in driver
* phy_write(phydev, 7, 33) : write page=12, reg=7, val=33
*
* or simply
* reimplemented. For now it should be sufficient.
*/
-struct rtmdio_port {
+struct rtmd_port {
int page;
bool raw;
u8 smi_addr;
u8 smi_bus;
};
-struct rtmdio_bus {
+struct rtmd_bus {
bool is_c45;
struct mii_bus *mii_bus;
};
-struct rtmdio_ctrl {
+struct rtmd_ctrl {
struct mutex lock;
struct regmap *map;
- const struct rtmdio_config *cfg;
- struct rtmdio_port port[RTMDIO_MAX_PORTS];
- struct rtmdio_bus bus[RTMDIO_MAX_SMI_BUSSES];
- DECLARE_BITMAP(valid_ports, RTMDIO_MAX_PORTS);
+ const struct rtmd_config *cfg;
+ struct rtmd_port port[RTMD_MAX_PORTS];
+ struct rtmd_bus bus[RTMD_MAX_SMI_BUSSES];
+ DECLARE_BITMAP(valid_ports, RTMD_MAX_PORTS);
};
-struct rtmdio_chan {
- struct rtmdio_ctrl *ctrl;
+struct rtmd_chan {
+ struct rtmd_ctrl *ctrl;
u8 smi_bus;
};
-struct rtmdio_command_data {
+struct rtmd_command_data {
u32 brdcast;
u32 c22_adr;
u32 c45_adr;
u32 mask_hi;
};
-struct rtmdio_config {
+struct rtmd_config {
u32 cmd_fail;
u32 cmd_io_shift;
- struct rtmdio_command_data cmd_regs;
+ struct rtmd_command_data cmd_regs;
int bus_map_base;
u16 num_busses;
u16 num_pages;
int port_map_base;
int (*read_c22)(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val);
int (*read_c45)(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val);
- int (*setup_ctrl)(struct rtmdio_ctrl *ctrl);
- int (*setup_polling)(struct rtmdio_ctrl *ctrl);
+ int (*setup_ctrl)(struct rtmd_ctrl *ctrl);
+ int (*setup_polling)(struct rtmd_ctrl *ctrl);
int (*write_c22)(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val);
int (*write_c45)(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val);
};
-struct rtmdio_phy_info {
+struct rtmd_phy_info {
int mac_type;
bool has_giga_lite;
bool has_res_reg;
unsigned int poll_lpa_1000;
};
-static inline struct rtmdio_ctrl *rtmdio_ctrl_from_bus(struct mii_bus *bus)
+static inline struct rtmd_ctrl *rtmd_ctrl_from_bus(struct mii_bus *bus)
{
- return ((struct rtmdio_chan *)bus->priv)->ctrl;
+ return ((struct rtmd_chan *)bus->priv)->ctrl;
}
-static int rtmdio_phy_to_port(struct mii_bus *bus, int phy)
+static int rtmd_phy_to_port(struct mii_bus *bus, int phy)
{
- struct rtmdio_chan *chan = bus->priv;
- struct rtmdio_ctrl *ctrl = chan->ctrl;
+ struct rtmd_chan *chan = bus->priv;
+ struct rtmd_ctrl *ctrl = chan->ctrl;
int pn;
for_each_port(ctrl, pn)
return -ENOENT;
}
-static int rtmdio_run_cmd(struct mii_bus *bus, u32 cmd,
- struct rtmdio_command_data *cmd_data, u32 *val)
+static int rtmd_run_cmd(struct mii_bus *bus, u32 cmd,
+ struct rtmd_command_data *cmd_data, u32 *val)
{
- struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
+ struct rtmd_ctrl *ctrl = rtmd_ctrl_from_bus(bus);
u32 cmdstate;
int ret;
/* C22 data and command bits share the same register. */
ret = regmap_write(ctrl->map, ctrl->cfg->cmd_regs.c22_adr,
- cmd_data->c22_adr | cmd | RTMDIO_RUN);
+ cmd_data->c22_adr | cmd | RTMD_RUN);
if (ret)
return ret;
ret = regmap_read_poll_timeout(ctrl->map, ctrl->cfg->cmd_regs.c22_adr,
- cmdstate, !(cmdstate & RTMDIO_RUN), 20, 500000);
+ cmdstate, !(cmdstate & RTMD_RUN), 20, 500000);
if (ret) {
dev_warn_once(&bus->dev, "access timed out\n");
return ret;
return ret;
}
-static int rtmdio_838x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
+static int rtmd_838x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
{
- struct rtmdio_command_data cmd_data = {
- .c22_adr = RTMDIO_838X_C22_DATA(page, reg),
+ struct rtmd_command_data cmd_data = {
+ .c22_adr = RTMD_838X_C22_DATA(page, reg),
.io_data = pn,
};
- return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_READ_C22, &cmd_data, val);
+ return rtmd_run_cmd(bus, RTMD_838X_CMD_READ_C22, &cmd_data, val);
}
-static int rtmdio_838x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
+static int rtmd_838x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
{
- struct rtmdio_command_data cmd_data = {
- .c22_adr = RTMDIO_838X_C22_DATA(page, reg),
+ struct rtmd_command_data cmd_data = {
+ .c22_adr = RTMD_838X_C22_DATA(page, reg),
.io_data = val,
.mask_lo = BIT(pn),
};
- return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C22, &cmd_data, NULL);
+ return rtmd_run_cmd(bus, RTMD_838X_CMD_WRITE_C22, &cmd_data, NULL);
}
-static int rtmdio_838x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
+static int rtmd_838x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
{
- struct rtmdio_command_data cmd_data = {
- .c45_adr = RTMDIO_C45_DATA(devnum, regnum),
+ struct rtmd_command_data cmd_data = {
+ .c45_adr = RTMD_C45_DATA(devnum, regnum),
.io_data = pn,
};
- return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_READ_C45, &cmd_data, val);
+ return rtmd_run_cmd(bus, RTMD_838X_CMD_READ_C45, &cmd_data, val);
}
-static int rtmdio_838x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
+static int rtmd_838x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
{
- struct rtmdio_command_data cmd_data = {
- .c45_adr = RTMDIO_C45_DATA(devnum, regnum),
+ struct rtmd_command_data cmd_data = {
+ .c45_adr = RTMD_C45_DATA(devnum, regnum),
.io_data = val,
.mask_lo = BIT(pn),
};
- return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C45, &cmd_data, NULL);
+ return rtmd_run_cmd(bus, RTMD_838X_CMD_WRITE_C45, &cmd_data, NULL);
}
-static int rtmdio_839x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
+static int rtmd_839x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
{
- struct rtmdio_command_data cmd_data = {
- .c22_adr = RTMDIO_839X_C22_DATA(page, reg),
- .ex_page = RTMDIO_839X_PHYREG_SKIP_EXT_PAGE,
+ struct rtmd_command_data cmd_data = {
+ .c22_adr = RTMD_839X_C22_DATA(page, reg),
+ .ex_page = RTMD_839X_PHYREG_SKIP_EXT_PAGE,
.io_data = pn,
};
- return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_READ_C22, &cmd_data, val);
+ return rtmd_run_cmd(bus, RTMD_839X_CMD_READ_C22, &cmd_data, val);
}
-static int rtmdio_839x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
+static int rtmd_839x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
{
- struct rtmdio_command_data cmd_data = {
- .c22_adr = RTMDIO_839X_C22_DATA(page, reg),
- .ex_page = RTMDIO_839X_PHYREG_SKIP_EXT_PAGE,
+ struct rtmd_command_data cmd_data = {
+ .c22_adr = RTMD_839X_C22_DATA(page, reg),
+ .ex_page = RTMD_839X_PHYREG_SKIP_EXT_PAGE,
.io_data = val,
.mask_lo = (u32)(BIT_ULL(pn)),
.mask_hi = (u32)(BIT_ULL(pn) >> 32),
};
- return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C22, &cmd_data, NULL);
+ return rtmd_run_cmd(bus, RTMD_839X_CMD_WRITE_C22, &cmd_data, NULL);
}
-static int rtmdio_839x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
+static int rtmd_839x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
{
- struct rtmdio_command_data cmd_data = {
- .c45_adr = RTMDIO_C45_DATA(devnum, regnum),
+ struct rtmd_command_data cmd_data = {
+ .c45_adr = RTMD_C45_DATA(devnum, regnum),
.io_data = pn,
};
- return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_READ_C45, &cmd_data, val);
+ return rtmd_run_cmd(bus, RTMD_839X_CMD_READ_C45, &cmd_data, val);
}
-static int rtmdio_839x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
+static int rtmd_839x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
{
- struct rtmdio_command_data cmd_data = {
- .c45_adr = RTMDIO_C45_DATA(devnum, regnum),
+ struct rtmd_command_data cmd_data = {
+ .c45_adr = RTMD_C45_DATA(devnum, regnum),
.io_data = val,
.mask_lo = (u32)(BIT_ULL(pn)),
.mask_hi = (u32)(BIT_ULL(pn) >> 32),
};
- return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C45, &cmd_data, NULL);
+ return rtmd_run_cmd(bus, RTMD_839X_CMD_WRITE_C45, &cmd_data, NULL);
}
-static int rtmdio_930x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
+static int rtmd_930x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
{
- struct rtmdio_command_data cmd_data = {
- .c22_adr = RTMDIO_930X_C22_DATA(page, reg),
+ struct rtmd_command_data cmd_data = {
+ .c22_adr = RTMD_930X_C22_DATA(page, reg),
.io_data = pn,
};
- return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_READ_C22, &cmd_data, val);
+ return rtmd_run_cmd(bus, RTMD_930X_CMD_READ_C22, &cmd_data, val);
}
-static int rtmdio_930x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
+static int rtmd_930x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
{
- struct rtmdio_command_data cmd_data = {
- .c22_adr = RTMDIO_930X_C22_DATA(page, reg),
+ struct rtmd_command_data cmd_data = {
+ .c22_adr = RTMD_930X_C22_DATA(page, reg),
.io_data = val,
.mask_lo = BIT(pn),
};
- return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C22, &cmd_data, NULL);
+ return rtmd_run_cmd(bus, RTMD_930X_CMD_WRITE_C22, &cmd_data, NULL);
}
-static int rtmdio_930x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
+static int rtmd_930x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
{
- struct rtmdio_command_data cmd_data = {
- .c45_adr = RTMDIO_C45_DATA(devnum, regnum),
+ struct rtmd_command_data cmd_data = {
+ .c45_adr = RTMD_C45_DATA(devnum, regnum),
.io_data = pn,
};
- return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_READ_C45, &cmd_data, val);
+ return rtmd_run_cmd(bus, RTMD_930X_CMD_READ_C45, &cmd_data, val);
}
-static int rtmdio_930x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
+static int rtmd_930x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
{
- struct rtmdio_command_data cmd_data = {
- .c45_adr = RTMDIO_C45_DATA(devnum, regnum),
+ struct rtmd_command_data cmd_data = {
+ .c45_adr = RTMD_C45_DATA(devnum, regnum),
.io_data = val,
.mask_lo = BIT(pn),
};
- return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C45, &cmd_data, NULL);
+ return rtmd_run_cmd(bus, RTMD_930X_CMD_WRITE_C45, &cmd_data, NULL);
}
-static int rtmdio_931x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
+static int rtmd_931x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
{
- struct rtmdio_command_data cmd_data = {
- .brdcast = RTMDIO_931X_SMI_INDRT_PORT(pn),
- .c22_adr = RTMDIO_931X_C22_DATA(page, reg),
+ struct rtmd_command_data cmd_data = {
+ .brdcast = RTMD_931X_SMI_INDRT_PORT(pn),
+ .c22_adr = RTMD_931X_C22_DATA(page, reg),
};
- return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_READ_C22, &cmd_data, val);
+ return rtmd_run_cmd(bus, RTMD_931X_CMD_READ_C22, &cmd_data, val);
}
-static int rtmdio_931x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
+static int rtmd_931x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
{
- struct rtmdio_command_data cmd_data = {
- .c22_adr = RTMDIO_931X_C22_DATA(page, reg),
+ struct rtmd_command_data cmd_data = {
+ .c22_adr = RTMD_931X_C22_DATA(page, reg),
.mask_lo = (u32)(BIT_ULL(pn)),
.mask_hi = (u32)(BIT_ULL(pn) >> 32),
.io_data = val,
};
- return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C22, &cmd_data, NULL);
+ return rtmd_run_cmd(bus, RTMD_931X_CMD_WRITE_C22, &cmd_data, NULL);
}
-static int rtmdio_931x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
+static int rtmd_931x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
{
- struct rtmdio_command_data cmd_data = {
- .brdcast = RTMDIO_931X_SMI_INDRT_PORT(pn),
- .c45_adr = RTMDIO_C45_DATA(devnum, regnum),
+ struct rtmd_command_data cmd_data = {
+ .brdcast = RTMD_931X_SMI_INDRT_PORT(pn),
+ .c45_adr = RTMD_C45_DATA(devnum, regnum),
};
- return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_READ_C45, &cmd_data, val);
+ return rtmd_run_cmd(bus, RTMD_931X_CMD_READ_C45, &cmd_data, val);
}
-static int rtmdio_931x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
+static int rtmd_931x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
{
- struct rtmdio_command_data cmd_data = {
- .c45_adr = RTMDIO_C45_DATA(devnum, regnum),
+ struct rtmd_command_data cmd_data = {
+ .c45_adr = RTMD_C45_DATA(devnum, regnum),
.mask_lo = (u32)(BIT_ULL(pn)),
.mask_hi = (u32)(BIT_ULL(pn) >> 32),
.io_data = val,
};
- return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C45, &cmd_data, NULL);
+ return rtmd_run_cmd(bus, RTMD_931X_CMD_WRITE_C45, &cmd_data, NULL);
}
-static int rtmdio_read_c45(struct mii_bus *bus, int phy, int devnum, int regnum)
+static int rtmd_read_c45(struct mii_bus *bus, int phy, int devnum, int regnum)
{
- struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
+ struct rtmd_ctrl *ctrl = rtmd_ctrl_from_bus(bus);
int ret, pn, val = 0;
- pn = rtmdio_phy_to_port(bus, phy);
+ pn = rtmd_phy_to_port(bus, phy);
if (pn < 0)
return pn;
return ret ? ret : val;
}
-static int rtmdio_read_c22(struct mii_bus *bus, int phy, int regnum)
+static int rtmd_read_c22(struct mii_bus *bus, int phy, int regnum)
{
- struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
+ struct rtmd_ctrl *ctrl = rtmd_ctrl_from_bus(bus);
int ret, pn, val = 0;
- pn = rtmdio_phy_to_port(bus, phy);
+ pn = rtmd_phy_to_port(bus, phy);
if (pn < 0)
return pn;
guard(mutex)(&ctrl->lock);
- if (regnum == RTMDIO_PAGE_SELECT &&
- ctrl->port[pn].page != RTMDIO_RAW_PAGE(ctrl->cfg->num_pages))
+ if (regnum == RTMD_PAGE_SELECT &&
+ ctrl->port[pn].page != RTMD_RAW_PAGE(ctrl->cfg->num_pages))
return ctrl->port[pn].page;
- ctrl->port[pn].raw = (ctrl->port[pn].page == RTMDIO_RAW_PAGE(ctrl->cfg->num_pages));
+ ctrl->port[pn].raw = (ctrl->port[pn].page == RTMD_RAW_PAGE(ctrl->cfg->num_pages));
ret = (*ctrl->cfg->read_c22)(bus, pn, ctrl->port[pn].page, regnum, &val);
dev_dbg(&bus->dev, "rd_PHY(phy=0x%02x, pag=0x%04x, reg=0x%04x) = 0x%04x, ret = %d\n",
return ret ? ret : val;
}
-static int rtmdio_write_c45(struct mii_bus *bus, int phy, int devnum, int regnum, u16 val)
+static int rtmd_write_c45(struct mii_bus *bus, int phy, int devnum, int regnum, u16 val)
{
- struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
+ struct rtmd_ctrl *ctrl = rtmd_ctrl_from_bus(bus);
int ret, pn;
- pn = rtmdio_phy_to_port(bus, phy);
+ pn = rtmd_phy_to_port(bus, phy);
if (pn < 0)
return pn;
return ret;
}
-static int rtmdio_write_c22(struct mii_bus *bus, int phy, int regnum, u16 val)
+static int rtmd_write_c22(struct mii_bus *bus, int phy, int regnum, u16 val)
{
- struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
+ struct rtmd_ctrl *ctrl = rtmd_ctrl_from_bus(bus);
int ret, page, pn;
- pn = rtmdio_phy_to_port(bus, phy);
+ pn = rtmd_phy_to_port(bus, phy);
if (pn < 0)
return pn;
guard(mutex)(&ctrl->lock);
page = ctrl->port[pn].page;
- if (regnum == RTMDIO_PAGE_SELECT)
+ if (regnum == RTMD_PAGE_SELECT)
ctrl->port[pn].page = val;
if (!ctrl->port[pn].raw &&
- (regnum != RTMDIO_PAGE_SELECT || page == RTMDIO_RAW_PAGE(ctrl->cfg->num_pages))) {
- ctrl->port[pn].raw = (page == RTMDIO_RAW_PAGE(ctrl->cfg->num_pages));
+ (regnum != RTMD_PAGE_SELECT || page == RTMD_RAW_PAGE(ctrl->cfg->num_pages))) {
+ ctrl->port[pn].raw = (page == RTMD_RAW_PAGE(ctrl->cfg->num_pages));
ret = (*ctrl->cfg->write_c22)(bus, pn, page, regnum, val);
dev_dbg(&bus->dev,
return 0;
}
-static int rtmdio_poll_port(struct rtmdio_ctrl *ctrl, int pn, bool active)
+static int rtmd_poll_port(struct rtmd_ctrl *ctrl, int pn, bool active)
{
return regmap_assign_bits(ctrl->map, ctrl->cfg->poll_ctrl + (pn / 32) * 4,
BIT(pn % 32), active);
}
-static int rtmdio_disable_polling(struct rtmdio_ctrl *ctrl)
+static int rtmd_disable_polling(struct rtmd_ctrl *ctrl)
{
int pn, ret;
for (pn = 0; pn < ctrl->cfg->num_ports; pn++) {
- ret = rtmdio_poll_port(ctrl, pn, false);
+ ret = rtmd_poll_port(ctrl, pn, false);
if (ret)
return ret;
}
return 0;
}
-static int rtmdio_setup_smi_topology(struct rtmdio_ctrl *ctrl)
+static int rtmd_setup_smi_topology(struct rtmd_ctrl *ctrl)
{
u32 reg, mask, val, pn;
int ret;
return 0;
}
-static u32 rtmdio_get_phy_id(struct phy_device *phydev)
+static u32 rtmd_get_phy_id(struct phy_device *phydev)
{
if (!phydev)
return 0;
return phydev->phy_id;
}
-static int rtmdio_get_phy_info(struct rtmdio_ctrl *ctrl, int pn, struct rtmdio_phy_info *phyinfo)
+static int rtmd_get_phy_info(struct rtmd_ctrl *ctrl, int pn, struct rtmd_phy_info *phyinfo)
{
struct mii_bus *bus;
u32 smi_addr, phyid;
bus = ctrl->bus[ctrl->port[pn].smi_bus].mii_bus;
smi_addr = ctrl->port[pn].smi_addr;
- phyid = rtmdio_get_phy_id(mdiobus_get_phy(bus, smi_addr));
+ phyid = rtmd_get_phy_id(mdiobus_get_phy(bus, smi_addr));
/* Determine PHY specific characteristics for polling fine tuning */
memset(phyinfo, 0, sizeof(*phyinfo));
switch (phyid) {
- case RTMDIO_PHY_AQR113C_A:
- case RTMDIO_PHY_AQR113C_B:
- case RTMDIO_PHY_AQR813:
- phyinfo->mac_type = RTMDIO_PHY_MAC_2G_PLUS;
- phyinfo->poll_duplex = RTMDIO_PHY_POLL_MMD(1, 0x0000, 8);
- phyinfo->poll_adv_1000 = RTMDIO_PHY_POLL_MMD(7, 0xc400, 15);
- phyinfo->poll_lpa_1000 = RTMDIO_PHY_POLL_MMD(7, 0xe820, 15);
+ case RTMD_PHY_AQR113C_A:
+ case RTMD_PHY_AQR113C_B:
+ case RTMD_PHY_AQR813:
+ phyinfo->mac_type = RTMD_PHY_MAC_2G_PLUS;
+ phyinfo->poll_duplex = RTMD_PHY_POLL_MMD(1, 0x0000, 8);
+ phyinfo->poll_adv_1000 = RTMD_PHY_POLL_MMD(7, 0xc400, 15);
+ phyinfo->poll_lpa_1000 = RTMD_PHY_POLL_MMD(7, 0xe820, 15);
break;
- case RTMDIO_PHY_RTL8218D:
- case RTMDIO_PHY_RTL8218E:
- phyinfo->mac_type = RTMDIO_PHY_MAC_1G;
+ case RTMD_PHY_RTL8218D:
+ case RTMD_PHY_RTL8218E:
+ phyinfo->mac_type = RTMD_PHY_MAC_1G;
phyinfo->has_giga_lite = true;
break;
- case RTMDIO_PHY_RTL8226:
- case RTMDIO_PHY_RTL8221B_VB_CG:
- case RTMDIO_PHY_RTL8221B_VM_CG:
- case RTMDIO_PHY_RTL8224:
- phyinfo->mac_type = RTMDIO_PHY_MAC_2G_PLUS;
+ case RTMD_PHY_RTL8226:
+ case RTMD_PHY_RTL8221B_VB_CG:
+ case RTMD_PHY_RTL8221B_VM_CG:
+ case RTMD_PHY_RTL8224:
+ phyinfo->mac_type = RTMD_PHY_MAC_2G_PLUS;
phyinfo->has_giga_lite = true;
- phyinfo->poll_duplex = RTMDIO_PHY_POLL_MMD(31, 0xa400, 8);
- phyinfo->poll_adv_1000 = RTMDIO_PHY_POLL_MMD(31, 0xa412, 9);
- phyinfo->poll_lpa_1000 = RTMDIO_PHY_POLL_MMD(31, 0xa414, 11);
+ phyinfo->poll_duplex = RTMD_PHY_POLL_MMD(31, 0xa400, 8);
+ phyinfo->poll_adv_1000 = RTMD_PHY_POLL_MMD(31, 0xa412, 9);
+ phyinfo->poll_lpa_1000 = RTMD_PHY_POLL_MMD(31, 0xa414, 11);
break;
- case RTMDIO_PHY_RTL8261:
- phyinfo->mac_type = RTMDIO_PHY_MAC_2G_PLUS;
+ case RTMD_PHY_RTL8261:
+ phyinfo->mac_type = RTMD_PHY_MAC_2G_PLUS;
phyinfo->has_giga_lite = true;
phyinfo->has_res_reg = true;
break;
return 0;
}
-static int rtmdio_838x_setup_ctrl(struct rtmdio_ctrl *ctrl)
+static int rtmd_838x_setup_ctrl(struct rtmd_ctrl *ctrl)
{
/*
* PHY_PATCH_DONE enables phy control via SoC. This is required for phy access,
* including patching. Must always be set before the phys are probed.
*/
- return regmap_set_bits(ctrl->map, RTMDIO_838X_SMI_GLB_CTRL,
- RTMDIO_838X_SMI_GLB_PHY_PATCH_DONE);
+ return regmap_set_bits(ctrl->map, RTMD_838X_SMI_GLB_CTRL,
+ RTMD_838X_SMI_GLB_PHY_PATCH_DONE);
}
-static int rtmdio_838x_setup_polling(struct rtmdio_ctrl *ctrl)
+static int rtmd_838x_setup_polling(struct rtmd_ctrl *ctrl)
{
/*
* Control bits EX_PHY_MAN_xxx have an important effect on the detection of the media
* give the real media status (0=copper, 1=fibre). For now assume that if address 24 is
* PHY driven, it must be a combo PHY and media detection is needed.
*/
- return regmap_assign_bits(ctrl->map, RTMDIO_838X_SMI_GLB_CTRL,
- RTMDIO_838X_SMI_GLB_PHY_MAN_24_27,
+ return regmap_assign_bits(ctrl->map, RTMD_838X_SMI_GLB_CTRL,
+ RTMD_838X_SMI_GLB_PHY_MAN_24_27,
test_bit(24, ctrl->valid_ports));
}
-static int rtmdio_930x_setup_ctrl(struct rtmdio_ctrl *ctrl)
+static int rtmd_930x_setup_ctrl(struct rtmd_ctrl *ctrl)
{
int ret;
/* Define C22/C45 bus feature set */
for (int smi_bus = 0; smi_bus < ctrl->cfg->num_busses; smi_bus++) {
- ret = regmap_assign_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL,
- RTMDIO_930X_SMI_GLB_INTF_SEL(smi_bus),
+ ret = regmap_assign_bits(ctrl->map, RTMD_930X_SMI_GLB_CTRL,
+ RTMD_930X_SMI_GLB_INTF_SEL(smi_bus),
ctrl->bus[smi_bus].is_c45);
if (ret)
return ret;
return 0;
}
-static int rtmdio_930x_set_port_ability(struct rtmdio_ctrl *ctrl, u32 pn, u32 ability)
+static int rtmd_930x_set_port_ability(struct rtmd_ctrl *ctrl, u32 pn, u32 ability)
{
u32 mask;
if (pn < 24)
- mask = RTMDIO_930X_SMI_MAC_TYPE_P0_23(pn);
+ mask = RTMD_930X_SMI_MAC_TYPE_P0_23(pn);
else if (pn < 28)
- mask = RTMDIO_930X_SMI_MAC_TYPE_P24_27(pn);
+ mask = RTMD_930X_SMI_MAC_TYPE_P24_27(pn);
else
return -EINVAL;
- return regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_MAC_TYPE_CTRL,
+ return regmap_update_bits(ctrl->map, RTMD_930X_SMI_MAC_TYPE_CTRL,
mask, ability << __ffs(mask));
}
-static int rtmdio_930x_setup_polling(struct rtmdio_ctrl *ctrl)
+static int rtmd_930x_setup_polling(struct rtmd_ctrl *ctrl)
{
- struct rtmdio_phy_info phyinfo;
+ struct rtmd_phy_info phyinfo;
int ret;
u32 pn;
/* set all ports to "SerDes driven" */
for (pn = 0; pn < ctrl->cfg->num_ports; pn++) {
- ret = rtmdio_930x_set_port_ability(ctrl, pn, RTMDIO_PHY_MAC_SDS);
+ ret = rtmd_930x_set_port_ability(ctrl, pn, RTMD_PHY_MAC_SDS);
if (ret)
return ret;
}
/* Define PHY specific polling parameters */
for_each_port(ctrl, pn) {
- if (rtmdio_get_phy_info(ctrl, pn, &phyinfo))
+ if (rtmd_get_phy_info(ctrl, pn, &phyinfo))
continue;
/* set port to "PHY driven" */
- ret = rtmdio_930x_set_port_ability(ctrl, pn, phyinfo.mac_type);
+ ret = rtmd_930x_set_port_ability(ctrl, pn, phyinfo.mac_type);
if (ret)
return ret;
/* polling via standard or resolution register */
- ret = regmap_assign_bits(ctrl->map, RTMDIO_930X_SMI_GLB_CTRL,
- RTMDIO_930X_SMI_GLB_POLL_SEL(ctrl->port[pn].smi_bus),
+ ret = regmap_assign_bits(ctrl->map, RTMD_930X_SMI_GLB_CTRL,
+ RTMD_930X_SMI_GLB_POLL_SEL(ctrl->port[pn].smi_bus),
phyinfo.has_res_reg);
if (ret)
return ret;
/* proprietary Realtek 1G/2.5 lite polling */
- ret = regmap_assign_bits(ctrl->map, RTMDIO_930X_SMI_PRVTE_POLLING_CTRL,
- BIT(pn), phyinfo.has_giga_lite);
+ ret = regmap_assign_bits(ctrl->map, RTMD_930X_SMI_PRVTE_POLLING_CTRL,
+ BIT(pn), phyinfo.has_giga_lite);
if (ret)
return ret;
continue;
/* Unique 10G polling setup enforced by hardware design. Always same 10G PHYs. */
- ret = regmap_write(ctrl->map, RTMDIO_930X_SMI_10G_POLLING_REG0_CFG,
+ ret = regmap_write(ctrl->map, RTMD_930X_SMI_10G_POLLING_REG0_CFG,
phyinfo.poll_duplex);
if (ret)
return ret;
- ret = regmap_write(ctrl->map, RTMDIO_930X_SMI_10G_POLLING_REG9_CFG,
+ ret = regmap_write(ctrl->map, RTMD_930X_SMI_10G_POLLING_REG9_CFG,
phyinfo.poll_adv_1000);
if (ret)
return ret;
- ret = regmap_write(ctrl->map, RTMDIO_930X_SMI_10G_POLLING_REG10_CFG,
+ ret = regmap_write(ctrl->map, RTMD_930X_SMI_10G_POLLING_REG10_CFG,
phyinfo.poll_lpa_1000);
if (ret)
return ret;
return 0;
}
-static int rtmdio_931x_setup_ctrl(struct rtmdio_ctrl *ctrl)
+static int rtmd_931x_setup_ctrl(struct rtmd_ctrl *ctrl)
{
int ret;
/* Define C22/C45 bus feature set (bit 1 of SMI_SETx_FMT_SEL) */
for (int smi_bus = 0; smi_bus < ctrl->cfg->num_busses; smi_bus++) {
- ret = regmap_assign_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL1,
- RTMDIO_931X_SMI_GLB_FMT_SEL_C45(smi_bus),
+ ret = regmap_assign_bits(ctrl->map, RTMD_931X_SMI_GLB_CTRL1,
+ RTMD_931X_SMI_GLB_FMT_SEL_C45(smi_bus),
ctrl->bus[smi_bus].is_c45);
if (ret)
return ret;
return 0;
}
-static int rtmdio_931x_set_port_ability(struct rtmdio_ctrl *ctrl, u32 pn, u32 ability)
+static int rtmd_931x_set_port_ability(struct rtmd_ctrl *ctrl, u32 pn, u32 ability)
{
u32 mask;
if (pn < ctrl->cfg->num_ports)
- mask = RTMDIO_931X_SMI_PHY_ABLTY_MASK(pn);
+ mask = RTMD_931X_SMI_PHY_ABLTY_MASK(pn);
else
return -EINVAL;
- return regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL(pn),
+ return regmap_update_bits(ctrl->map, RTMD_931X_SMI_PHY_ABLTY_GET_SEL(pn),
mask, ability << __ffs(mask));
}
-static int rtmdio_931x_setup_polling(struct rtmdio_ctrl *ctrl)
+static int rtmd_931x_setup_polling(struct rtmd_ctrl *ctrl)
{
- struct rtmdio_phy_info phyinfo;
+ struct rtmd_phy_info phyinfo;
int ret;
u32 pn;
/* set all ports to "SerDes driven" */
for (pn = 0; pn < ctrl->cfg->num_ports; pn++) {
- ret = rtmdio_931x_set_port_ability(ctrl, pn, RTMDIO_931X_SMI_PHY_ABLTY_SDS);
+ ret = rtmd_931x_set_port_ability(ctrl, pn, RTMD_931X_SMI_PHY_ABLTY_SDS);
if (ret)
return ret;
}
for_each_port(ctrl, pn) {
u8 smi_bus = ctrl->port[pn].smi_bus;
- if (rtmdio_get_phy_info(ctrl, pn, &phyinfo))
+ if (rtmd_get_phy_info(ctrl, pn, &phyinfo))
continue;
/* set port to "PHY driven" */
- ret = rtmdio_931x_set_port_ability(ctrl, pn, RTMDIO_931X_SMI_PHY_ABLTY_MDIO);
+ ret = rtmd_931x_set_port_ability(ctrl, pn, RTMD_931X_SMI_PHY_ABLTY_MDIO);
if (ret)
return ret;
- ret = regmap_assign_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL0,
- RTMDIO_931X_SMI_GLB_PRVTE0_POLL(smi_bus),
+ ret = regmap_assign_bits(ctrl->map, RTMD_931X_SMI_GLB_CTRL0,
+ RTMD_931X_SMI_GLB_PRVTE0_POLL(smi_bus),
phyinfo.has_res_reg);
if (ret)
return ret;
- ret = regmap_assign_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL0,
- RTMDIO_931X_SMI_GLB_PRVTE1_POLL(smi_bus),
+ ret = regmap_assign_bits(ctrl->map, RTMD_931X_SMI_GLB_CTRL0,
+ RTMD_931X_SMI_GLB_PRVTE1_POLL(smi_bus),
phyinfo.force_res);
if (ret)
return ret;
/* polling std. or proprietary format (bit 0 of SMI_SETx_FMT_SEL) */
- ret = regmap_assign_bits(ctrl->map, RTMDIO_931X_SMI_GLB_CTRL1,
- RTMDIO_931X_SMI_GLB_FMT_SEL_FRC(smi_bus),
+ ret = regmap_assign_bits(ctrl->map, RTMD_931X_SMI_GLB_CTRL1,
+ RTMD_931X_SMI_GLB_FMT_SEL_FRC(smi_bus),
phyinfo.force_res);
if (ret)
return ret;
continue;
/* Unique 10G polling setup enforced by hardware design. Always same 10G PHYs. */
- ret = regmap_write(ctrl->map, RTMDIO_931X_SMI_10GPHY_POLLING_SEL2,
+ ret = regmap_write(ctrl->map, RTMD_931X_SMI_10GPHY_POLLING_SEL2,
phyinfo.poll_duplex);
if (ret)
return ret;
- ret = regmap_write(ctrl->map, RTMDIO_931X_SMI_10GPHY_POLLING_SEL3,
+ ret = regmap_write(ctrl->map, RTMD_931X_SMI_10GPHY_POLLING_SEL3,
phyinfo.poll_adv_1000);
if (ret)
return ret;
- ret = regmap_write(ctrl->map, RTMDIO_931X_SMI_10GPHY_POLLING_SEL4,
+ ret = regmap_write(ctrl->map, RTMD_931X_SMI_10GPHY_POLLING_SEL4,
phyinfo.poll_lpa_1000);
if (ret)
return ret;
return 0;
}
-static int rtmdio_map_ports(struct device *dev)
+static int rtmd_map_ports(struct device *dev)
{
- struct rtmdio_ctrl *ctrl = dev_get_drvdata(dev);
+ struct rtmd_ctrl *ctrl = dev_get_drvdata(dev);
int smi_bus, smi_addr, pn;
struct device_node *switch_node __free(device_node) =
return 0;
}
-static int rtmdio_probe_one(struct device *dev, struct rtmdio_ctrl *ctrl,
+static int rtmd_probe_one(struct device *dev, struct rtmd_ctrl *ctrl,
struct fwnode_handle *node)
{
- struct rtmdio_chan *chan;
+ struct rtmd_chan *chan;
struct mii_bus *bus;
int smi_bus, ret;
chan->smi_bus = smi_bus;
bus->name = "Realtek MDIO bus";
- bus->read = rtmdio_read_c22;
- bus->write = rtmdio_write_c22;
- bus->read_c45 = rtmdio_read_c45;
- bus->write_c45 = rtmdio_write_c45;
+ bus->read = rtmd_read_c22;
+ bus->write = rtmd_write_c22;
+ bus->read_c45 = rtmd_read_c45;
+ bus->write_c45 = rtmd_write_c45;
bus->parent = dev;
snprintf(bus->id, MII_BUS_ID_SIZE, "realtek-mdio-%d", smi_bus);
return 0;
}
-static int rtmdio_probe(struct platform_device *pdev)
+static int rtmd_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct rtmdio_ctrl *ctrl;
+ struct rtmd_ctrl *ctrl;
int ret;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
return ret;
platform_set_drvdata(pdev, ctrl);
- ctrl->cfg = (const struct rtmdio_config *)device_get_match_data(dev);
+ ctrl->cfg = (const struct rtmd_config *)device_get_match_data(dev);
ctrl->map = syscon_node_to_regmap(pdev->dev.of_node->parent);
if (IS_ERR(ctrl->map))
return PTR_ERR(ctrl->map);
- ret = rtmdio_disable_polling(ctrl);
+ ret = rtmd_disable_polling(ctrl);
if (ret)
return ret;
- ret = rtmdio_map_ports(dev);
+ ret = rtmd_map_ports(dev);
if (ret)
return ret;
- ret = rtmdio_setup_smi_topology(ctrl);
+ ret = rtmd_setup_smi_topology(ctrl);
if (ret)
return ret;
}
device_for_each_child_node_scoped(dev, child) {
- ret = rtmdio_probe_one(dev, ctrl, child);
+ ret = rtmd_probe_one(dev, ctrl, child);
if (ret)
return ret;
}
return 0;
}
-static const struct rtmdio_config rtmdio_838x_cfg = {
- .cmd_fail = RTMDIO_838X_CMD_FAIL,
- .cmd_io_shift = RTMDIO_DATA_IN_HI_OUT_LOW,
+static const struct rtmd_config rtmd_838x_cfg = {
+ .cmd_fail = RTMD_838X_CMD_FAIL,
+ .cmd_io_shift = RTMD_DATA_IN_HI_OUT_LOW,
.cmd_regs = {
- .c22_adr = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1,
- .c45_adr = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3,
- .mask_lo = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0,
- .io_data = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2,
+ .c22_adr = RTMD_838X_SMI_ACCESS_PHY_CTRL_1,
+ .c45_adr = RTMD_838X_SMI_ACCESS_PHY_CTRL_3,
+ .mask_lo = RTMD_838X_SMI_ACCESS_PHY_CTRL_0,
+ .io_data = RTMD_838X_SMI_ACCESS_PHY_CTRL_2,
},
- .num_busses = RTMDIO_838X_NUM_BUSSES,
- .num_pages = RTMDIO_838X_NUM_PAGES,
- .num_ports = RTMDIO_838X_NUM_PORTS,
- .poll_ctrl = RTMDIO_838X_SMI_POLL_CTRL,
- .port_map_base = RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL,
- .read_c22 = rtmdio_838x_read_c22,
- .read_c45 = rtmdio_838x_read_c45,
- .setup_ctrl = rtmdio_838x_setup_ctrl,
- .setup_polling = rtmdio_838x_setup_polling,
- .write_c22 = rtmdio_838x_write_c22,
- .write_c45 = rtmdio_838x_write_c45,
+ .num_busses = RTMD_838X_NUM_BUSSES,
+ .num_pages = RTMD_838X_NUM_PAGES,
+ .num_ports = RTMD_838X_NUM_PORTS,
+ .poll_ctrl = RTMD_838X_SMI_POLL_CTRL,
+ .port_map_base = RTMD_838X_SMI_PORT0_5_ADDR_CTRL,
+ .read_c22 = rtmd_838x_read_c22,
+ .read_c45 = rtmd_838x_read_c45,
+ .setup_ctrl = rtmd_838x_setup_ctrl,
+ .setup_polling = rtmd_838x_setup_polling,
+ .write_c22 = rtmd_838x_write_c22,
+ .write_c45 = rtmd_838x_write_c45,
};
-static const struct rtmdio_config rtmdio_839x_cfg = {
- .cmd_fail = RTMDIO_839X_CMD_FAIL,
- .cmd_io_shift = RTMDIO_DATA_IN_HI_OUT_LOW,
+static const struct rtmd_config rtmd_839x_cfg = {
+ .cmd_fail = RTMD_839X_CMD_FAIL,
+ .cmd_io_shift = RTMD_DATA_IN_HI_OUT_LOW,
.cmd_regs = {
- .brdcast = RTMDIO_839X_BCAST_PHYID_CTRL,
- .c22_adr = RTMDIO_839X_PHYREG_ACCESS_CTRL,
- .c45_adr = RTMDIO_839X_PHYREG_MMD_CTRL,
- .ex_page = RTMDIO_839X_PHYREG_CTRL,
- .mask_lo = RTMDIO_839X_PHYREG_PORT_CTRL(0),
- .mask_hi = RTMDIO_839X_PHYREG_PORT_CTRL(1),
- .io_data = RTMDIO_839X_PHYREG_DATA_CTRL,
+ .brdcast = RTMD_839X_BCAST_PHYID_CTRL,
+ .c22_adr = RTMD_839X_PHYREG_ACCESS_CTRL,
+ .c45_adr = RTMD_839X_PHYREG_MMD_CTRL,
+ .ex_page = RTMD_839X_PHYREG_CTRL,
+ .mask_lo = RTMD_839X_PHYREG_PORT_CTRL(0),
+ .mask_hi = RTMD_839X_PHYREG_PORT_CTRL(1),
+ .io_data = RTMD_839X_PHYREG_DATA_CTRL,
},
- .num_busses = RTMDIO_839X_NUM_BUSSES,
- .num_pages = RTMDIO_839X_NUM_PAGES,
- .num_ports = RTMDIO_839X_NUM_PORTS,
- .poll_ctrl = RTMDIO_839X_SMI_PORT_POLLING_CTRL,
- .read_c22 = rtmdio_839x_read_c22,
- .read_c45 = rtmdio_839x_read_c45,
- .write_c22 = rtmdio_839x_write_c22,
- .write_c45 = rtmdio_839x_write_c45,
+ .num_busses = RTMD_839X_NUM_BUSSES,
+ .num_pages = RTMD_839X_NUM_PAGES,
+ .num_ports = RTMD_839X_NUM_PORTS,
+ .poll_ctrl = RTMD_839X_SMI_PORT_POLLING_CTRL,
+ .read_c22 = rtmd_839x_read_c22,
+ .read_c45 = rtmd_839x_read_c45,
+ .write_c22 = rtmd_839x_write_c22,
+ .write_c45 = rtmd_839x_write_c45,
};
-static const struct rtmdio_config rtmdio_930x_cfg = {
- .cmd_fail = RTMDIO_930X_CMD_FAIL,
- .cmd_io_shift = RTMDIO_DATA_IN_HI_OUT_LOW,
+static const struct rtmd_config rtmd_930x_cfg = {
+ .cmd_fail = RTMD_930X_CMD_FAIL,
+ .cmd_io_shift = RTMD_DATA_IN_HI_OUT_LOW,
.cmd_regs = {
- .c22_adr = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1,
- .c45_adr = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3,
- .mask_lo = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0,
- .io_data = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2,
+ .c22_adr = RTMD_930X_SMI_ACCESS_PHY_CTRL_1,
+ .c45_adr = RTMD_930X_SMI_ACCESS_PHY_CTRL_3,
+ .mask_lo = RTMD_930X_SMI_ACCESS_PHY_CTRL_0,
+ .io_data = RTMD_930X_SMI_ACCESS_PHY_CTRL_2,
},
- .bus_map_base = RTMDIO_930X_SMI_PORT0_15_POLLING_SEL,
- .num_busses = RTMDIO_930X_NUM_BUSSES,
- .num_pages = RTMDIO_930X_NUM_PAGES,
- .num_ports = RTMDIO_930X_NUM_PORTS,
- .poll_ctrl = RTMDIO_930X_SMI_POLL_CTRL,
- .port_map_base = RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL,
- .read_c22 = rtmdio_930x_read_c22,
- .read_c45 = rtmdio_930x_read_c45,
- .setup_ctrl = rtmdio_930x_setup_ctrl,
- .setup_polling = rtmdio_930x_setup_polling,
- .write_c22 = rtmdio_930x_write_c22,
- .write_c45 = rtmdio_930x_write_c45,
+ .bus_map_base = RTMD_930X_SMI_PORT0_15_POLLING_SEL,
+ .num_busses = RTMD_930X_NUM_BUSSES,
+ .num_pages = RTMD_930X_NUM_PAGES,
+ .num_ports = RTMD_930X_NUM_PORTS,
+ .poll_ctrl = RTMD_930X_SMI_POLL_CTRL,
+ .port_map_base = RTMD_930X_SMI_PORT0_5_ADDR_CTRL,
+ .read_c22 = rtmd_930x_read_c22,
+ .read_c45 = rtmd_930x_read_c45,
+ .setup_ctrl = rtmd_930x_setup_ctrl,
+ .setup_polling = rtmd_930x_setup_polling,
+ .write_c22 = rtmd_930x_write_c22,
+ .write_c45 = rtmd_930x_write_c45,
};
-static const struct rtmdio_config rtmdio_931x_cfg = {
- .cmd_fail = RTMDIO_931X_CMD_FAIL,
- .cmd_io_shift = RTMDIO_DATA_IN_LOW_OUT_HI,
+static const struct rtmd_config rtmd_931x_cfg = {
+ .cmd_fail = RTMD_931X_CMD_FAIL,
+ .cmd_io_shift = RTMD_DATA_IN_LOW_OUT_HI,
.cmd_regs = {
- .brdcast = RTMDIO_931X_SMI_INDRT_ACCESS_BC,
- .c22_adr = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0,
- .c45_adr = RTMDIO_931X_SMI_INDRT_ACCESS_MMD,
- .ex_page = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1,
- .mask_lo = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2(0),
- .mask_hi = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2(1),
- .io_data = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3,
+ .brdcast = RTMD_931X_SMI_INDRT_ACCESS_BC,
+ .c22_adr = RTMD_931X_SMI_INDRT_ACCESS_CTRL_0,
+ .c45_adr = RTMD_931X_SMI_INDRT_ACCESS_MMD,
+ .ex_page = RTMD_931X_SMI_INDRT_ACCESS_CTRL_1,
+ .mask_lo = RTMD_931X_SMI_INDRT_ACCESS_CTRL_2(0),
+ .mask_hi = RTMD_931X_SMI_INDRT_ACCESS_CTRL_2(1),
+ .io_data = RTMD_931X_SMI_INDRT_ACCESS_CTRL_3,
},
- .bus_map_base = RTMDIO_931X_SMI_PORT_POLLING_SEL,
- .num_busses = RTMDIO_931X_NUM_BUSSES,
- .num_pages = RTMDIO_931X_NUM_PAGES,
- .num_ports = RTMDIO_931X_NUM_PORTS,
- .poll_ctrl = RTMDIO_931X_SMI_PORT_POLLING_CTRL,
- .port_map_base = RTMDIO_931X_SMI_PORT_ADDR_CTRL,
- .read_c22 = rtmdio_931x_read_c22,
- .read_c45 = rtmdio_931x_read_c45,
- .setup_ctrl = rtmdio_931x_setup_ctrl,
- .setup_polling = rtmdio_931x_setup_polling,
- .write_c22 = rtmdio_931x_write_c22,
- .write_c45 = rtmdio_931x_write_c45,
+ .bus_map_base = RTMD_931X_SMI_PORT_POLLING_SEL,
+ .num_busses = RTMD_931X_NUM_BUSSES,
+ .num_pages = RTMD_931X_NUM_PAGES,
+ .num_ports = RTMD_931X_NUM_PORTS,
+ .poll_ctrl = RTMD_931X_SMI_PORT_POLLING_CTRL,
+ .port_map_base = RTMD_931X_SMI_PORT_ADDR_CTRL,
+ .read_c22 = rtmd_931x_read_c22,
+ .read_c45 = rtmd_931x_read_c45,
+ .setup_ctrl = rtmd_931x_setup_ctrl,
+ .setup_polling = rtmd_931x_setup_polling,
+ .write_c22 = rtmd_931x_write_c22,
+ .write_c45 = rtmd_931x_write_c45,
};
-static const struct of_device_id rtmdio_ids[] = {
+static const struct of_device_id rtmd_ids[] = {
{
.compatible = "realtek,rtl8380-mdio",
- .data = &rtmdio_838x_cfg,
+ .data = &rtmd_838x_cfg,
},
{
.compatible = "realtek,rtl8392-mdio",
- .data = &rtmdio_839x_cfg,
+ .data = &rtmd_839x_cfg,
},
{
.compatible = "realtek,rtl9301-mdio",
- .data = &rtmdio_930x_cfg,
+ .data = &rtmd_930x_cfg,
},
{
.compatible = "realtek,rtl9311-mdio",
- .data = &rtmdio_931x_cfg,
+ .data = &rtmd_931x_cfg,
},
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, rtmdio_ids);
+MODULE_DEVICE_TABLE(of, rtmd_ids);
-static struct platform_driver rtmdio_driver = {
- .probe = rtmdio_probe,
+static struct platform_driver rtmd_driver = {
+ .probe = rtmd_probe,
.driver = {
.name = "mdio-rtl-otto",
- .of_match_table = rtmdio_ids,
+ .of_match_table = rtmd_ids,
},
};
-module_platform_driver(rtmdio_driver);
+module_platform_driver(rtmd_driver);
MODULE_AUTHOR("Markus Stockhausen <markus.stockhausen@gmx.de>");
MODULE_DESCRIPTION("Realtek Otto MDIO driver");
projects / thirdparty / openwrt.git / commitdiff
