;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+;; Code organisation:
+;
+;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are
+;; a little blurry.
+;;
+;; Therefore code is organised by the following rough principles:
+;;
+;; - aarch64.md: For shared parts of the architecture (such as defining
+;; registers and constants) and for instructions that operate on non-SIMD
+;; registers.
+;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD
+;; registers.
+;; - aarch64-sve.md for SVE instructions that are pre SVE2.
+;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with
+;; non-streaming mode. This usually means it uses the ZA or ZT register.
+;; - aarch64-sve2.md for any scalable SIMD instruction that either is
+;; streaming compatible, or theoretically could be later.
+
;; The following define_subst rules are used to produce patterns representing
;; the implicit zeroing effect of 64-bit Advanced SIMD operations, in effect
;; a vec_concat with zeroes. The order of the vec_concat operands differs
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+;; Code organisation:
+;
+;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are
+;; a little blurry.
+;;
+;; Therefore code is organised by the following rough principles:
+;;
+;; - aarch64.md: For shared parts of the architecture (such as defining
+;; registers and constants) and for instructions that operate on non-SIMD
+;; registers.
+;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD
+;; registers.
+;; - aarch64-sve.md for SVE instructions that are pre SVE2.
+;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with
+;; non-streaming mode. This usually means it uses the ZA or ZT register.
+;; - aarch64-sve2.md for any scalable SIMD instruction that either is
+;; streaming compatible, or theoretically could be later.
+
;; The file is organised into the following sections (search for the full
;; line):
;;
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+/* Code organisation:
+
+ The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get
+ a little blurry.
+
+ Therefore code is organised by the following rough principles:
+
+ - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally
+ incompatible with non-streaming mode. This usually means it uses the ZA
+ or ZT register.
+ - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode
+ intrinsic, but either is non-streaming compatible, or theoretically could
+ be later.
+ - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2.
+ - aarch64-sve-builtins.def for common data types and group definitions used
+ across all files. */
+
#define REQUIRED_EXTENSIONS ssve (0)
DEF_SVE_FUNCTION (svabd, binary_opt_n, all_arith, mxz)
DEF_SVE_FUNCTION (svabs, unary, all_float_and_signed, mxz)
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+/* Code organisation:
+
+ The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get
+ a little blurry.
+
+ Therefore code is organised by the following rough principles:
+
+ - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally
+ incompatible with non-streaming mode. This usually means it uses the ZA
+ or ZT register.
+ - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode
+ intrinsic, but either is non-streaming compatible, or theoretically could
+ be later.
+ - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2.
+ - aarch64-sve-builtins.def for common data types and group definitions used
+ across all files. */
#ifndef DEF_SME_FUNCTION_GS
#define DEF_SME_FUNCTION_GS(NAME, SHAPE, TYPES, GROUPS, PREDS) \
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+/* Code organisation:
+
+ The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get
+ a little blurry.
+
+ Therefore code is organised by the following rough principles:
+
+ - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally
+ incompatible with non-streaming mode. This usually means it uses the ZA
+ or ZT register.
+ - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode
+ intrinsic, but either is non-streaming compatible, or theoretically could
+ be later.
+ - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2.
+ - aarch64-sve-builtins.def for common data types and group definitions used
+ across all files. */
+
#define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2, 0)
DEF_SVE_FUNCTION (svaba, ternary_opt_n, all_integer, none)
DEF_SVE_FUNCTION (svabalb, ternary_long_opt_n, hsd_integer, none)
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+/* Code organisation:
+
+ The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get
+ a little blurry.
+
+ Therefore code is organised by the following rough principles:
+
+ - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally
+ incompatible with non-streaming mode. This usually means it uses the ZA
+ or ZT register.
+ - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode
+ intrinsic, but either is non-streaming compatible, or theoretically could
+ be later.
+ - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2.
+ - aarch64-sve-builtins.def for common data types and group definitions used
+ across all files. */
+
#ifndef DEF_SVE_MODE
#define DEF_SVE_MODE(A, B, C, D)
#endif
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+;; Code organisation:
+;
+;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are
+;; a little blurry.
+;;
+;; Therefore code is organised by the following rough principles:
+;;
+;; - aarch64.md: For shared parts of the architecture (such as defining
+;; registers and constants) and for instructions that operate on non-SIMD
+;; registers.
+;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD
+;; registers.
+;; - aarch64-sve.md for SVE instructions that are pre SVE2.
+;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with
+;; non-streaming mode. This usually means it uses the ZA or ZT register.
+;; - aarch64-sve2.md for any scalable SIMD instruction that either is
+;; streaming compatible, or theoretically could be later.
+
;; The file is organised into the following sections (search for the full
;; line):
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+;
+;; Code organisation:
+;
+;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are
+;; a little blurry.
+;;
+;; Therefore code is organised by the following rough principles:
+;;
+;; - aarch64.md: For shared parts of the architecture (such as defining
+;; registers and constants) and for instructions that operate on non-SIMD
+;; registers.
+;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD
+;; registers.
+;; - aarch64-sve.md for SVE instructions that are pre SVE2.
+;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with
+;; non-streaming mode. This usually means it uses the ZA or ZT register.
+;; - aarch64-sve2.md for any scalable SIMD instruction that either is
+;; streaming compatible, or theoretically could be later.
;; The file is organised into the following sections (search for the full
;; line):
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+;; Code organisation:
+;
+;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are
+;; a little blurry.
+;;
+;; Therefore code is organised by the following rough principles:
+;;
+;; - aarch64.md: For shared parts of the architecture (such as defining
+;; registers and constants) and for instructions that operate on non-SIMD
+;; registers.
+;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD
+;; registers.
+;; - aarch64-sve.md for SVE instructions that are pre SVE2.
+;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with
+;; non-streaming mode. This usually means it uses the ZA or ZT register.
+;; - aarch64-sve2.md for any scalable SIMD instruction that either is
+;; streaming compatible, or theoretically could be later.
+
;; Register numbers
(define_constants
[
projects / thirdparty / gcc.git / commitdiff
