drm/i915/cx0: Fix HDMI FRL clock rates

HDMI FRL clock rates are incorrectly defined. Fix these
rates.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-10-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 26d3d41d41a732eb04241149f4724352f223997e..eda0e176b8beb44e158b0b44a23e93c774d45092 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1924,7 +1924,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
-       .clock = 3000000,
+       .clock = 300000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */
@@ -1949,7 +1949,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
-       .clock = 6000000,
+       .clock = 600000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */
@@ -1974,7 +1974,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
-       .clock = 8000000,
+       .clock = 800000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */
@@ -1999,7 +1999,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
-       .clock = 10000000,
+       .clock = 1000000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */
@@ -2024,7 +2024,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
-       .clock = 12000000,
+       .clock = 1200000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */