drivers: usb: dwc3: Add delay after core soft reset

Add a 100 ms delay after clearing the core soft reset bit to ensure
the DWC3 controller has sufficient time to complete its reset
sequence before subsequent register accesses.

Without this delay, USB initialization can fail on some Qualcomm
platforms, particularly when using super-speed capable PHYs like
the QMP USB3-DP Combo PHY on SC7280/QCM6490.

Taken from Linux commit f88359e1588b ("usb: dwc3: core: Do core softreset when switch mode")

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20251203110735.1959862-3-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 65c4d1a4e6f41fead44f49bf1dc184d8b1cd8fd0..0dee14c8b592b0f71fe193494e67452d9b6f8790 100644 (file)
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -106,6 +106,8 @@ done:
        if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
                mdelay(50);
 
+       mdelay(100);
+
        return 0;
 }