arm64: versal: Drop static DDR and PCIe MMU mappings

AM011 Versal ACAP TRM, Table 43, defines:
- 0x006_0000_0000 - 0x007_FFFF_FFFF PCIe region 1
- 0x008_0000_0000 - 0x00F_FFFF_FFFF DDR controller 0 region 1
- 0x040_0000_0000 - 0x04F_FFFF_FFFF HBM0
- 0x050_0000_0000 - 0x05F_FFFF_FFFF HBM1
- 0x060_0000_0000 - 0x06F_FFFF_FFFF HBM2
- 0x070_0000_0000 - 0x07F_FFFF_FFFF HBM3
- 0x080_0000_0000 - 0x0BF_FFFF_FFFF PCIe region 2
- 0x0C0_0000_0000 - 0x0FF_FFFF_FFFF DDR controller 0 region 2

The old static normal-memory mapping spans PCIe, while DDR coverage is
already populated later from the DRAM banks discovered by mem_map_fill().
Drop the stale static mapping so the MMU table matches the Versal address
map. Also matting was using wrong attributes.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6fad36f9e7abdfee2fd29943f3a5b63d1421eaf9.1781179823.git.michal.simek@amd.com

diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
index 0dd5cc153c47708d0fa4a44bd5d73c073a6c3b8d..7ffd35fe89cbe4dc7419fecd43f89bd19f5533eb 100644 (file)
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016 - 2018 Xilinx, Inc.
+ * (C) Copyright 2026, Advanced Micro Devices, Inc.
+ *
  * Michal Simek <michal.simek@amd.com>
  */
 
@@ -16,7 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define VERSAL_MEM_MAP_USED    5
+#define VERSAL_MEM_MAP_USED    3
 
 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
 
@@ -44,26 +46,13 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
                         PTE_BLOCK_NON_SHARE |
                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       }, {
+       }, { /* FPD_AXI_PL_high */
                .virt = 0x400000000UL,
                .phys = 0x400000000UL,
                .size = 0x200000000UL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
                         PTE_BLOCK_NON_SHARE |
                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       }, {
-               .virt = 0x600000000UL,
-               .phys = 0x600000000UL,
-               .size = 0x800000000UL,
-               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-                        PTE_BLOCK_INNER_SHARE
-       }, {
-               .virt = 0xe00000000UL,
-               .phys = 0xe00000000UL,
-               .size = 0xf200000000UL,
-               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-                        PTE_BLOCK_NON_SHARE |
-                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
        }
 };