arm64: zynqmp: Move board_early_init_r clock setup to mach code

board_early_init_r() programmed the system timestamp counter directly
with readl()/writel() in board code. This is SoC register setup rather
than board policy, and similar code exists across the Xilinx SoCs.

Move it into zynqmp_timer_setup() in arch/arm/mach-zynqmp so the board
hook only keeps the EL3 guard and calls the helper. The asm/arch/clk.h
include (for zynqmp_get_system_timer_freq()) moves to cpu.c along with
the code.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/2d8f2419fab314b4ff8fd53b846e1dd6151586d3.1782219202.git.michal.simek@amd.com

diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 3dc47e5d48e47e62adf781962114c00b385ce2a6..e6f2e0b3ee09b172f15c29e61115ce2c645ced7f 100644 (file)
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -8,6 +8,7 @@
 #include <time.h>
 #include <linux/errno.h>
 #include <linux/types.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/armv8/mmu.h>
@@ -234,6 +235,27 @@ int zynqmp_mmio_read(const u32 address, u32 *value)
        return ret;
 }
 
+void zynqmp_timer_setup(void)
+{
+       u32 val;
+
+       val = readl(&crlapb_base->timestamp_ref_ctrl);
+       val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+
+       if (!val) {
+               val = readl(&crlapb_base->timestamp_ref_ctrl);
+               val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+               writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+               /* Program freq register in System counter */
+               writel(zynqmp_get_system_timer_freq(),
+                      &iou_scntr_secure->base_frequency_id_register);
+               /* And enable system counter */
+               writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+                      &iou_scntr_secure->counter_control_register);
+       }
+}
+
 U_BOOT_DRVINFO(soc_xilinx_zynqmp) = {
        .name = "soc_xilinx_zynqmp",
 };

diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index b6a41df1da47eb2ba04cb14f0d15801265b61edb..723e7593cf7bc378bf7a335e6f8dbd353ac3dbc8 100644 (file)
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -54,5 +54,7 @@ void mem_map_fill(void);
 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
 void tcm_init(enum tcm_mode mode);
 #endif
+/* EL3 clock/timer register setup, called from board_early_init_r() */
+void zynqmp_timer_setup(void);
 
 #endif /* _ASM_ARCH_SYS_PROTO_H */

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index a12c039d8c955f077549b63255b4c6c756be3e57..5d13881f3ec243a8efc7b339352f9d22eb4c45bc 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -24,7 +24,6 @@
 #include <malloc.h>
 #include <memalign.h>
 #include <wdt.h>
-#include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/psu_init_gpl.h>
@@ -214,26 +213,11 @@ int board_init(void)
 
 int board_early_init_r(void)
 {
-       u32 val;
-
        if (current_el() != 3)
                return 0;
 
-       val = readl(&crlapb_base->timestamp_ref_ctrl);
-       val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
-
-       if (!val) {
-               val = readl(&crlapb_base->timestamp_ref_ctrl);
-               val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
-               writel(val, &crlapb_base->timestamp_ref_ctrl);
+       zynqmp_timer_setup();
 
-               /* Program freq register in System counter */
-               writel(zynqmp_get_system_timer_freq(),
-                      &iou_scntr_secure->base_frequency_id_register);
-               /* And enable system counter */
-               writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
-                      &iou_scntr_secure->counter_control_register);
-       }
        return 0;
 }